Innovative Silicon’s Z-RAM meets low voltage and bulk silicon requirements of DRAM memory manufacturers

SANTA CLARA, USA: Innovative Silicon Inc. (ISi) developer of the Z-RAM zero-capacitor, floating body (FB) memory technology, announced two major breakthroughs to its Z-RAM technology.

First, bit cell operating voltage has been reduced to below one volt (1V), making it the industry’s lowest-voltage FB memory bit cell and the first to be on-par with traditional DRAM voltages. Second, Z-RAM technology is now constructed on bulk silicon – without the requirement for expensive silicon on insulator (SOI) substrates – by using the 3D transistor structures preferred by the major DRAM manufacturers.

With these enhancements, which have been substantiated on a test chip manufactured by Hynix Semiconductor, ISi has demonstrated that the Z-RAM technology is the only DRAM memory replacement technology that is lower-cost than traditional DRAM at the latest sub-40nm nodes. Moreover, the Z-RAM technology can meet DRAM requirements for low power consumption, low-voltage operation, and the latest Double Data Rate (DDRx) performance levels.

“Conventional DRAM has been the low cost, random-access memory technology for 40 years, but the memory industry is on the verge of transitioning to the capacitor-free Z-RAM technology.”

“We are very excited about the upgrades to our Z-RAM technology, as they tackle, head-on, the requirements of the large memory manufacturers to have the technology available on bulk silicon and with lower costs than any other DRAM technology – including conventional DRAM,” said Mark-Eric Jones, president and CEO of Innovative Silicon. “Conventional DRAM has been the low cost, random-access memory technology for 40 years, but the memory industry is on the verge of transitioning to the capacitor-free Z-RAM technology.”

Pierre Fazan, chairman and CTO of ISi adds: “The Z-RAM technology now has all of the key ingredients to fully replace stand-alone DRAM. It is implemented on bulk silicon and has demonstrated cell operating voltages below 1V with no degradation to its multi-second static retention time, and delivers greater than a 1000x improvement in dynamic or ‘disturb’ retention time. The Z-RAM technology’s operating voltage is now 50 to 75 percent lower than any other floating body or thyristor memory announced to date, and it is the only FB memory technology to cover the entire ITRS memory roadmap.”

Dr. Sungjoo Hong, VP of DRAM R&D at Hynix Semiconductor, said: “Our collaborative efforts with ISi continue to be fruitful. The advances in power and voltage demonstrated in our 54nm test chips show that the Z-RAM technology has solved the most challenging issues we have seen with floating-body memories. These results validate that the Z-RAM technology has great potential to replace conventional DRAM over the next few memory generations.”

“The DRAM market, the largest of the memory markets, is facing phenomenal challenges in migrating to future process nodes,” said Jim Handy, of Objective Analysis.

“Floating body technology is poised to solve some of those challenges, and now with Z-RAM on bulk substrates and running at DRAM-level voltages, Innovative Silicon is in a good position to help the industry continue to deliver cost reductions consistent with Moore's Law.”

A paper jointly authored by Z-RAM licensee Hynix and ISi which describes the “Remarkable Low Voltage Operation of Z-RAM” has been submitted to the 2010 VLSI Technology Symposium. The paper will reveal more details of the cell operating voltages. Innovative Silicon will publish more details on lower-voltage operation later in 2010.