TSMC qualifies ATopTech’s Aprisa physical design solution for 40nm designs

SANTA CLARA, USA: ATopTech Inc., a primary technology leader in integrated circuit (IC) physical design solutions addressing the challenges of designing ICs at 65nm and below, announced that Aprisa, the company’s award-winning physical design solution, has been qualified for TSMC’s 40nm technology node, meeting the foundry’s requirements of placement, routing and transparent half node implementation.

Aprisa is a complete netlist-to-GDSII physical design solution, including floorplanning, placement, clock-tree synthesis and optimization, global and detailed routing, and an advanced, extremely fast timing engine to solve the complex timing issues associated with on chip variation (OCV) and multi-corner, multi-mode (MCMM) analysis.

Based on ATopTech’s Precision Optimization technology, Aprisa enables real design closure at smaller geometries through accurate timing correlation to industry sign-off tools. Aprisa uses state-of-the-art multi-threading and distributed processing technology to further speed up the process and avoid the exploding runtime issues associated with the variability in sub-micron designs.

“We have been pleased to work with ATopTech to qualify their digital implementation tools,” said S. T. Juang, senior director of Design Infrastructure Marketing at TSMC. “We look forward to continuing the collaboration to qualify Aprisa for the next technology node.”

“Aprisa has been successfully used by our customers in multiple 40nm design tapeouts,” said Dr. Ping-San Tzeng, ATopTech President and CTO. “Qualification by TSMC further confirms that our tools are production-ready for 40nm technologies, and gives customers even greater confidence that they can use Aprisa at this node and get excellent results.”