Magma announces Talus Design 1.1 and Talus RTL 1.1

SAN JOSE, USA: Magma Design Automation Inc. has announced the availability of Talus Design 1.1 and Talus RTL 1.1, Magma's full-chip synthesis products for advanced integrated circuits.

Capabilities in these new versions include GlassBox abstraction technology; enhanced optimization algorithms; RTL-to-GDSII reference flows for leading IP providers including ARM, MIPS and Imagination Technologies (see related announcement today); and additional interfaces for commonly used third-party design-for-test (DFT) and formal verification tools.

These enhanced synthesis products with new out-of-the box synthesis flows eliminate the need to develop customized scripts, significantly reducing the time and effort required to achieve timing, area and power goals.

"Design teams are facing increasing pressure to achieve more with less and to reduce design iterations and turnaround time while meeting performance objectives," said Premal Buch, general manager of Magma's Design Implementation Business Unit.

"To help designers address these challenges, Magma created version 1.1 of the Talus RTL-to-GDSII solution to deliver optimal quality of results out of the box. The recent enhancements to the Talus synthesis products provide designers with all the capabilities they need to generate high-quality netlists. Plus, the seamless integration with Magma's Talus Vortex implementation solution provides our users with increased confidence in achieving excellent results while shortening the time to final design closure."

"Using Talus Design within Magma's Talus implementation system has allowed us to significantly improve our productivity and time to market," said Andreas Olofsson, president of Adapteva, a manufacturer of multi-core processors that provide ultra low-energy solutions for high-performance portable applications.

"The Magma system delivers outstanding turnaround time; it enabled us to complete our most recent multimillion-gate 65-nanometer design in just six weeks. The tight link between Talus Design and Talus Vortex also provided the platform we needed to achieve an order of magnitude improvement in power and performance."

"We use Magma's complete RTL-to-GDSII solution, including Talus Design," said Mats Lafling, vice president of Engineering for Xelerated, a leading provider of high-performance network processors. "The tight integration between Talus Design and Talus Vortex helps us achieve our demanding high-performance targets quickly and efficiently."

Talus Design 1.1 and Talus RTL 1.1: Fast, high-capacity synthesis
Talus RTL and Talus Design are full-featured RTL logic synthesis solutions that optimize for power, area and timing, and generate both gate-level netlists or Magma Volcano databases for handoff. Talus RTL provides a complete RTL-to-netlist synthesis solution while Talus Design adds physical synthesis capabilities to deliver higher levels of predictability and performance.

Unlike traditional synthesis tools, a single Talus Design or Talus RTL license provides a fast, high-capacity synthesis solution with seamless scan insertion and scan optimization that supports VHDL, Verilog and System Verilog. The Magma synthesis tools are the first to support both the Common Power Format (CPF) and Unified Power Format (UPF) for specifying low-power design intent.

The new GlassBox capability in the enhanced Talus synthesis products creates logical abstractions for each block in the design. These abstractions retain only the critical information required for top-level synthesis, eliminating the need to re-synthesize each block, reducing turnaround time and minimizing hardware memory requirements.

Enhanced interoperability
To ensure high performance and highly testable systems on a chip (SoCs), Magma synthesis tools provide automatic scan insertion capabilities and include seamless interfaces to Mentor's industry-leading Tessent TestKompress automatic test pattern generation (ATPG) and Tessent LogicBIST built-in self test (BIST) products.

This ensures that test structures and their effects can be considered throughout the design flow to deliver the highest test coverage and efficiency with minimum impact to the design.

Today, most SoC designers use formal verification tools to confirm the final design is equivalent to the source RTL. The process of determining whether identified errors are actual problems often lengthens the design cycle. Talus Design 1.1 and Talus RTL 1.1 include output scripts that simplify and accelerate verification for users of Cadence's industry-leading equivalence checker, Conformal.

To further accelerate equivalence checking, scripts are included that identify swept or cloned flip-flops, scan-enable signals and integrated clock gates.

Talus Design 1.1 and Talus RTL 1.1 are available now.