USA: Analog Devices Inc. has introduced a digital audio bus technology capable of distributing audio and control data together with clock and power over a single, unshielded twisted-pair wire.
The AD2410 transceiver is the first in a family of devices that enables ADI’s new Automotive Audio Bus (A²B), which significantly reduces the weight of existing cable harnesses, resulting in improved vehicle fuel efficiency while delivering high fidelity audio. The AD2410 transceiver also eliminates the need for expensive microcontrollers with large memories that are required in existing digital bus architectures.
“As an early implementer of ADI’s A²B, Panasonic Automotive found the technology to significantly reduce cabling complexity and associated cost and weight of next-generation infotainment systems, key areas of focus for Panasonic’s OEM customers,” said Jonathan Lane, Group manager, Audio & Acoustics, part of Panasonic Automotive Systems Co. of America (PASA) Advanced Development Engineering.
“We believe A²B to be well suited to address applications such as microphone arrays and Active Noise Cancellation, a leading area of expertise for Panasonic that we expect to be an integral component of next-generation infotainment systems.”
Tuesday, October 28, 2014
Cadence announces Virtuoso Liberate AMS
SAN JOSE, USA: Cadence Design Systems Inc. announced the Cadence Virtuoso Liberate AMS characterization solution, the industry's first dynamic simulation characterization solution for mixed-signal blocks such as phase-locked loops (PLLs), data converters, high-speed transceivers and I/Os.
Built upon the proven Cadence Liberate characterization platform, Virtuoso Liberate AMS characterizes post-layout netlists of mixed-signal macros with millions of associated parasitic elements 20X faster than traditional "divide and conquer" FastSPICE simulation methods and with true SPICE accuracy to enable accurate system-on-chip (SoC) signoff.
With the increasing complexity of SoCs, and the industry shift towards intellectual property (IP) reuse and digital-on-top design flows for signoff with static analysis tools, Liberty representations are required for all blocks in the design including mixed-signal macros.
To simplify this process, Virtuoso Liberate AMS automates standard Liberty model creation for large mixed-signal macro blocks by capturing the interaction between digital and analog paths and modeling it into a final Liberty library.
To increase throughput and reduce turnaround time from weeks to hours, Virtuoso Liberate AMS integrates Cadence's advanced FastSPICE technology, Spectre® XPS, and employs a unique hybrid partitioning approach to statically identify required arcs and dynamically exercise them to characterize large mixed-signal blocks.
This hybrid partitioning approach identifies circuit activity at the block level to carve out a critical-path partition for each logic arc and then characterizes each partition with true SPICE accuracy to create highly accurate library models.
For custom circuit designers, Virtuoso Liberate AMS is integrated with Virtuoso Analog Design Environment XL and leverages Virtuoso Analog Design Environment XL testbenches and setup to quickly move from circuit design validation into library generation.
"Prior to using Virtuoso Liberate AMS, the characterization process for mixed-signal blocks was an error-prone manual process," said Darren Engelkemier, VP of Digital IC Engineering, of Aquantia Corp. "With Virtuoso Liberate AMS, our design teams were able to automate this task by eliminating netlist processing and getting more accurate and reliable data especially for our custom cells with non-standard structures at circuit-level."
"Cadence is committed to providing its customers with world-class simulation and characterization solutions," said Tom Beckley, senior VP, Custom IC and PCB Group at Cadence. "Virtuoso Liberate AMS extends the company's leadership in mixed-signal flows, and gives designers a powerful new solution to increase their productivity and reduce their time to market."
Built upon the proven Cadence Liberate characterization platform, Virtuoso Liberate AMS characterizes post-layout netlists of mixed-signal macros with millions of associated parasitic elements 20X faster than traditional "divide and conquer" FastSPICE simulation methods and with true SPICE accuracy to enable accurate system-on-chip (SoC) signoff.
With the increasing complexity of SoCs, and the industry shift towards intellectual property (IP) reuse and digital-on-top design flows for signoff with static analysis tools, Liberty representations are required for all blocks in the design including mixed-signal macros.
To simplify this process, Virtuoso Liberate AMS automates standard Liberty model creation for large mixed-signal macro blocks by capturing the interaction between digital and analog paths and modeling it into a final Liberty library.
To increase throughput and reduce turnaround time from weeks to hours, Virtuoso Liberate AMS integrates Cadence's advanced FastSPICE technology, Spectre® XPS, and employs a unique hybrid partitioning approach to statically identify required arcs and dynamically exercise them to characterize large mixed-signal blocks.
This hybrid partitioning approach identifies circuit activity at the block level to carve out a critical-path partition for each logic arc and then characterizes each partition with true SPICE accuracy to create highly accurate library models.
For custom circuit designers, Virtuoso Liberate AMS is integrated with Virtuoso Analog Design Environment XL and leverages Virtuoso Analog Design Environment XL testbenches and setup to quickly move from circuit design validation into library generation.
"Prior to using Virtuoso Liberate AMS, the characterization process for mixed-signal blocks was an error-prone manual process," said Darren Engelkemier, VP of Digital IC Engineering, of Aquantia Corp. "With Virtuoso Liberate AMS, our design teams were able to automate this task by eliminating netlist processing and getting more accurate and reliable data especially for our custom cells with non-standard structures at circuit-level."
"Cadence is committed to providing its customers with world-class simulation and characterization solutions," said Tom Beckley, senior VP, Custom IC and PCB Group at Cadence. "Virtuoso Liberate AMS extends the company's leadership in mixed-signal flows, and gives designers a powerful new solution to increase their productivity and reduce their time to market."
Monday, October 27, 2014
Cadence announces industry's first 25G Ethernet verification IP
SAN JOSE, USA: Cadence Design Systems Inc. announced the industry's first Verification IP (VIP) supporting the new 25-Gigabit (25G) Ethernet specification.
The 25G Ethernet specification extends the IEEE 802.3 standard to include operation at 25 Gb/s over copper cables and backplanes and increases server network throughput without using more interconnect lanes. Cadence 25G Ethernet VIP offers full verification support for both MAC and PHY designs while providing greater assurance that the design can operate as expected.
This new 25G Ethernet specification was created by the 25G Ethernet Consortium, with the goal of supporting an industry-standard, interoperable Ethernet specification that boosts performance and slashes interconnect cost. Cadence VIP also supports the 50G definition included in 25G Ethernet, which offers 2X port reduction and a 25 percent bandwidth improvement compared to 40G.
"The new 25G Ethernet specification and 50G definition enables the cost-efficient scaling of network bandwidth delivered to server and storage endpoints in next-generation cloud infrastructure," said Brad Booth, secretary, 25G Ethernet Consortium. "As one of the Consortium's early members, Cadence is enabling further adoption of the 25G Ethernet specification and 50G definition through the delivery of verification IP."
"25G Ethernet is an important new technology that is satisfying the ever-increasing need for scale in the datacenter in a cost-effective manner," said Martin Lund, senior VP of the IP Group at Cadence. "We continue to invest in VIP that accelerates industry adoption of new interface technology. Being first to market with VIP enables our customers to be first to market with their next-generation products."
The 25G Ethernet specification extends the IEEE 802.3 standard to include operation at 25 Gb/s over copper cables and backplanes and increases server network throughput without using more interconnect lanes. Cadence 25G Ethernet VIP offers full verification support for both MAC and PHY designs while providing greater assurance that the design can operate as expected.
This new 25G Ethernet specification was created by the 25G Ethernet Consortium, with the goal of supporting an industry-standard, interoperable Ethernet specification that boosts performance and slashes interconnect cost. Cadence VIP also supports the 50G definition included in 25G Ethernet, which offers 2X port reduction and a 25 percent bandwidth improvement compared to 40G.
"The new 25G Ethernet specification and 50G definition enables the cost-efficient scaling of network bandwidth delivered to server and storage endpoints in next-generation cloud infrastructure," said Brad Booth, secretary, 25G Ethernet Consortium. "As one of the Consortium's early members, Cadence is enabling further adoption of the 25G Ethernet specification and 50G definition through the delivery of verification IP."
"25G Ethernet is an important new technology that is satisfying the ever-increasing need for scale in the datacenter in a cost-effective manner," said Martin Lund, senior VP of the IP Group at Cadence. "We continue to invest in VIP that accelerates industry adoption of new interface technology. Being first to market with VIP enables our customers to be first to market with their next-generation products."
SMIC and ASML sign volume purchase agreement worth 450 million Euros
SHANGHAI, CHINA: Semiconductor Manufacturing International Corp. and ASML Holding N.V. announced the signing of a volume purchase agreement (VPA) that will provide SMIC with lithography systems from ASML.
The VPA which is worth approximately 450 million Euros and is part of a strategic partnership between the companies that will help facilitate the timely expansion of SMIC's advanced technology capacities.
Lithography is a critical step in the manufacturing of semiconductors and helps to create complex structures that make up the transistors on a wafer.
Under the agreement ASML will provide lithography tools such as the TWINSCAN NXT system designed for volume production of 300mm wafers at the 32nm node and beyond. Some of the specific benefits include increased productivity, unprecedented overlay performance and maximum image performance for each wafer.
"SMIC is the most advanced wafer foundry in China and ASML is the leading provider for lithography systems, and we believe that this partnership will complement both sides" said Dr. Tzu-Yin Chiu, CEO and executive director of SMIC. "We chose ASML as our provider due to their world-class products and services, and this cooperation will facilitate and strengthen the development of our advanced technologies."
"ASML is always committed to provide services that match the needs of our customers," said Peter Wennink, president and CEO of ASML.
"We are pleased to have SMIC as one of our customers, and the purchase of our lithography systems shows SMIC's recognition and trust in our technology. China is an important market for us and through this agreement, we hope to increase our presence and gain a stronger foothold with the Chinese customers. We believe this is a win-win solution where both parties can benefit from the deal."
Lilianne Ploumen, the Dutch Minister for Foreign Trade and Development Cooperation, accompanied by members of the Dutch Consulate, attended the signing ceremony as part of an economic mission to strengthen economic ties between the Netherlands and China.
At the ceremony, Minister Ploumen said: "China is an important market that continues to grow. The signing ceremony between SMIC and ASML marks the increasing high-tech cooperation between China and the Netherlands, and I sincerely hope that this continues to develop further."
The VPA which is worth approximately 450 million Euros and is part of a strategic partnership between the companies that will help facilitate the timely expansion of SMIC's advanced technology capacities.
Lithography is a critical step in the manufacturing of semiconductors and helps to create complex structures that make up the transistors on a wafer.
Under the agreement ASML will provide lithography tools such as the TWINSCAN NXT system designed for volume production of 300mm wafers at the 32nm node and beyond. Some of the specific benefits include increased productivity, unprecedented overlay performance and maximum image performance for each wafer.
"SMIC is the most advanced wafer foundry in China and ASML is the leading provider for lithography systems, and we believe that this partnership will complement both sides" said Dr. Tzu-Yin Chiu, CEO and executive director of SMIC. "We chose ASML as our provider due to their world-class products and services, and this cooperation will facilitate and strengthen the development of our advanced technologies."
"ASML is always committed to provide services that match the needs of our customers," said Peter Wennink, president and CEO of ASML.
"We are pleased to have SMIC as one of our customers, and the purchase of our lithography systems shows SMIC's recognition and trust in our technology. China is an important market for us and through this agreement, we hope to increase our presence and gain a stronger foothold with the Chinese customers. We believe this is a win-win solution where both parties can benefit from the deal."
Lilianne Ploumen, the Dutch Minister for Foreign Trade and Development Cooperation, accompanied by members of the Dutch Consulate, attended the signing ceremony as part of an economic mission to strengthen economic ties between the Netherlands and China.
At the ceremony, Minister Ploumen said: "China is an important market that continues to grow. The signing ceremony between SMIC and ASML marks the increasing high-tech cooperation between China and the Netherlands, and I sincerely hope that this continues to develop further."
SK Hynix accelerates memory development with Synopsys Verdi
MOUNTAIN VIEW, USA: Synopsys Inc. announced that SK Hynix Inc. has addressed their debug challenges by adopting the Synopsys VC Apps open application programming interfaces (APIs) to directly link their internally developed test generation technology to the industry-leading Synopsys Verdi debug solution and allow their design and verification teams to customize their debug experience and boost debug productivity.
Synopsys' VC Apps open APIs provide direct access to design environment and verification information stored in Verdi's open databases, which are in turn used by all leading simulation, emulation and formal verification solutions. With this native integration, SK Hynix engineers can save hours on each run and debug cycle.
"At SK Hynix, we had to find just the right balance of innovations from our technology partners with our own innovative processes in order to become the memory leader we are today," said Edward Kim, director of memory CAE at SK Hynix. "The productivity our engineers gain from deployment of VC Apps and standardized use of Verdi helps us to not only maintain that balance, but also reduce our costs and get working products to our customers faster."
Traditional methods for debugging data and results from internal or third-party tools involve either ad hoc manual steps and/or translation scripts that are both time-consuming and error-prone. VC Apps provides debug integration capabilities for CAD teams and tool developers, making it easy for individual users to further customize their debug flows and experience within Verdi.
With design and verification teams spending, on average, half of their time on debug, the time spent searching for commands and options or repeating common sequences of clicks and actions accumulates into substantial time and cost. The same APIs for Verdi databases and GUIs are accessible to all users, with clear open source examples and tutorials available on the VC Apps Exchange website and through the VC Apps Toolbox in Verdi.
"We collaborate closely with our semiconductor industry partners to ensure that debug remains as simple as possible despite the complexity of their chips and increased verification challenges," said Yu-Chin Hsu, VP of R&D, Synopsys Verification Group.
"We continue our significant investment in the open Verdi architecture, as well as in specialized technologies and methodologies for optimizing our customers' and partners' unique debug flows. VC Apps is one of the keys to unlocking the full power and flexibility that we have architected into both Verdi and now Verification Compiler product."
Synopsys' VC Apps open APIs provide direct access to design environment and verification information stored in Verdi's open databases, which are in turn used by all leading simulation, emulation and formal verification solutions. With this native integration, SK Hynix engineers can save hours on each run and debug cycle.
"At SK Hynix, we had to find just the right balance of innovations from our technology partners with our own innovative processes in order to become the memory leader we are today," said Edward Kim, director of memory CAE at SK Hynix. "The productivity our engineers gain from deployment of VC Apps and standardized use of Verdi helps us to not only maintain that balance, but also reduce our costs and get working products to our customers faster."
Traditional methods for debugging data and results from internal or third-party tools involve either ad hoc manual steps and/or translation scripts that are both time-consuming and error-prone. VC Apps provides debug integration capabilities for CAD teams and tool developers, making it easy for individual users to further customize their debug flows and experience within Verdi.
With design and verification teams spending, on average, half of their time on debug, the time spent searching for commands and options or repeating common sequences of clicks and actions accumulates into substantial time and cost. The same APIs for Verdi databases and GUIs are accessible to all users, with clear open source examples and tutorials available on the VC Apps Exchange website and through the VC Apps Toolbox in Verdi.
"We collaborate closely with our semiconductor industry partners to ensure that debug remains as simple as possible despite the complexity of their chips and increased verification challenges," said Yu-Chin Hsu, VP of R&D, Synopsys Verification Group.
"We continue our significant investment in the open Verdi architecture, as well as in specialized technologies and methodologies for optimizing our customers' and partners' unique debug flows. VC Apps is one of the keys to unlocking the full power and flexibility that we have architected into both Verdi and now Verification Compiler product."
Synopsys and Gowin Semiconductor ink multi-year OEM agreement for FPGA design software
MOUNTAIN VIEW, USA: Synopsys Inc. has announced a multi-year OEM agreement with Gowin Semiconductor for Synopsys Synplify Pro FPGA synthesis tools.
The agreement will enable Gowin customers to significantly improve synthesis runtimes and achieve higher quality of results for timing, area and power for Gowin GW2A/3S FPGAs. Gowin Semiconductor has partnered with Synopsys to integrate Synplify Pro into its GOWIN design suite for their GW2A/3S FPGAs.
"Our customers require a high performance, high-quality FPGA synthesis flow to help them implement their FPGA designs in hardware, while meeting tight project timelines," said Ning Song, chief technical officer and VP of FPGA software at Gowin Semiconductor.
"The integration of our FPGA software flow with Synplify Pro enables FPGA designers using our GW2A FPGA architecture to achieve the highest quality of results for timing, area and runtime."
Gowin's GW2A/3S FPGAs incorporate highly programmable logic, block SRAM and DSP blocks optimized for performance and power. The GW2A architecture is optimized with Synplify Pro synthesis software, providing designers with the highest performance results with fewer iterations.
Designers can take advantage of the wide range of device sizes and I/O capabilities to deliver products for consumer, industrial, communication and computing markets.
"Today's FPGA designs require advanced synthesis tools that deliver automation, faster turnaround times and more predictable timing closure," said John Koeter, VP of marketing for IP and prototyping at Synopsys.
"Synopsys Synplify FPGA synthesis software is the industry standard for producing high-performance, cost-effective FPGA designs. Integration of Synplify Pro with the GOWIN design suite will help Gowin customers quickly create optimized FPGA implementations that meet precise timing and quality requirements."
The agreement will enable Gowin customers to significantly improve synthesis runtimes and achieve higher quality of results for timing, area and power for Gowin GW2A/3S FPGAs. Gowin Semiconductor has partnered with Synopsys to integrate Synplify Pro into its GOWIN design suite for their GW2A/3S FPGAs.
"Our customers require a high performance, high-quality FPGA synthesis flow to help them implement their FPGA designs in hardware, while meeting tight project timelines," said Ning Song, chief technical officer and VP of FPGA software at Gowin Semiconductor.
"The integration of our FPGA software flow with Synplify Pro enables FPGA designers using our GW2A FPGA architecture to achieve the highest quality of results for timing, area and runtime."
Gowin's GW2A/3S FPGAs incorporate highly programmable logic, block SRAM and DSP blocks optimized for performance and power. The GW2A architecture is optimized with Synplify Pro synthesis software, providing designers with the highest performance results with fewer iterations.
Designers can take advantage of the wide range of device sizes and I/O capabilities to deliver products for consumer, industrial, communication and computing markets.
"Today's FPGA designs require advanced synthesis tools that deliver automation, faster turnaround times and more predictable timing closure," said John Koeter, VP of marketing for IP and prototyping at Synopsys.
"Synopsys Synplify FPGA synthesis software is the industry standard for producing high-performance, cost-effective FPGA designs. Integration of Synplify Pro with the GOWIN design suite will help Gowin customers quickly create optimized FPGA implementations that meet precise timing and quality requirements."
AMD Radeon supercharges Sid Meier’s Civilization: Beyond Earth with Mantle Graphics API
USA: AMD joins Firaxis Games in celebrating the release of Sid Meier’s Civilization: Beyond Earth, which features day-one support for AMD’s Mantle graphics API to enable top gaming performance for AMD Radeon graphics customers.
“AMD Radeon GPUs with Mantle are over a year ahead of other graphics companies in delivering high-throughput, high-efficiency graphics to gamers and developers,” said Matt Skynner, corporate VP and GM, Product and Platform Solutions Business Unit, AMD.
“As gamers settle in for a marathon session of Sid Meier’s Civilization: Beyond Earth, we’re proud that the potent combination of Mantle and the award-winning Graphics Core Next architecture effortlessly enable the definitive experience.”
Mantle is a “low-overhead” graphics API that can help improve performance for gamers by making better use of multi-core CPUs, streamlining game code execution, virtually eliminating software bottlenecks and utilizing GPU resources with incredible efficiency.
In performance testing, the AMD Radeon R9 290X GPU with Mantle rendered Sid Meier’s Civilization: Beyond Earth at higher frame rates than any other single-GPU graphics card. Gamers looking to secure Mantle’s blistering performance for their own empires can do so today with the purchase of an AMD Radeon R9 or R7 Series GPU starting at just $99.
“AMD Radeon GPUs with Mantle are over a year ahead of other graphics companies in delivering high-throughput, high-efficiency graphics to gamers and developers,” said Matt Skynner, corporate VP and GM, Product and Platform Solutions Business Unit, AMD.
“As gamers settle in for a marathon session of Sid Meier’s Civilization: Beyond Earth, we’re proud that the potent combination of Mantle and the award-winning Graphics Core Next architecture effortlessly enable the definitive experience.”
Mantle is a “low-overhead” graphics API that can help improve performance for gamers by making better use of multi-core CPUs, streamlining game code execution, virtually eliminating software bottlenecks and utilizing GPU resources with incredible efficiency.
In performance testing, the AMD Radeon R9 290X GPU with Mantle rendered Sid Meier’s Civilization: Beyond Earth at higher frame rates than any other single-GPU graphics card. Gamers looking to secure Mantle’s blistering performance for their own empires can do so today with the purchase of an AMD Radeon R9 or R7 Series GPU starting at just $99.
Mentor Graphics to host User2User 2014 India conference in Bangalore
BANGALORE, INDIA: Mentor Graphics Corp. announced that it will host its 10th annual User2User India conference on October 31, 2014 at Vivanta by Taj (the former Taj Residency), M.G.Road, Trinity Circle, Bangalore.
This year’s conference will feature keynote presentations from Walden C. Rhines, CEO and chairman, Mentor Graphics and Pradeep Vajram, president and CEO, Smartplay.
The conference includes an industry discussion on “Bringing together Indian and Multi-National Company Work - Cultures to Create the Next-Generation Organization” with panelists Pillalamarri Sridhar, MD, Maxlinear; Anuradha Srinivasan, research director, Intel Technologies India Pvt Ltd, Pradip A. Thaker, GM, India Operations and senior director (VLSI and H/W Engineering) for Geo Semiconductors; Himamshu Khasnis, CEO, Signalchip; and Walden C. Rhines, Mentor Graphics.
The Mentor Graphics User2User 2014 India conference is part of the annual Mentor Graphics international user conference series. This highly interactive, in-depth technical conference focuses on real world experiences using Mentor tools to design leading-edge products.
Attendees share with their colleagues their best practices, experiences, challenges, tips and tricks that they have learned using Mentor tools most effectively to design, develop and deploy high-quality products.
“Mentor’s User2User conference enables customers to network with one another, learn useful tips from company engineers and fellow users, and share best-practice methodologies,” said Hanns Windele, Mentor Graphics VP, Europe and India.
“Our goal is to provide users with everything they need to be productive with Mentor Graphics tools, and attendees report that they find their time at the event well spent.”
This year’s conference will feature keynote presentations from Walden C. Rhines, CEO and chairman, Mentor Graphics and Pradeep Vajram, president and CEO, Smartplay.
The conference includes an industry discussion on “Bringing together Indian and Multi-National Company Work - Cultures to Create the Next-Generation Organization” with panelists Pillalamarri Sridhar, MD, Maxlinear; Anuradha Srinivasan, research director, Intel Technologies India Pvt Ltd, Pradip A. Thaker, GM, India Operations and senior director (VLSI and H/W Engineering) for Geo Semiconductors; Himamshu Khasnis, CEO, Signalchip; and Walden C. Rhines, Mentor Graphics.
The Mentor Graphics User2User 2014 India conference is part of the annual Mentor Graphics international user conference series. This highly interactive, in-depth technical conference focuses on real world experiences using Mentor tools to design leading-edge products.
Attendees share with their colleagues their best practices, experiences, challenges, tips and tricks that they have learned using Mentor tools most effectively to design, develop and deploy high-quality products.
“Mentor’s User2User conference enables customers to network with one another, learn useful tips from company engineers and fellow users, and share best-practice methodologies,” said Hanns Windele, Mentor Graphics VP, Europe and India.
“Our goal is to provide users with everything they need to be productive with Mentor Graphics tools, and attendees report that they find their time at the event well spent.”
Worldwide semiconductor market is forecasted to be $325 billion in 2014, up 6.5 percent from 2013
USA: The World Semiconductor Trade Statistics (WSTS) has released its updated semiconductor market forecast. WSTS predicts that the world semiconductor market will reach $325 billion in 2014, up 6.5 percent from 2013.
All major product categories will show a high single digit growth rate, except microprocessors which will show a soft decline. The growth will be largely driven by smartphones, tablets and automotive.
The highest growth rates are shown for the Analog (9.1 percent) and Sensor (9.1 percent) category. By region, all regions except Japan will grow from 2013. Japan market is forecasted to decline from 2013 in US dollar basis due to JPY depreciation compared to 2013.
Solid growth for all product categories is expected to continue over the next two years, under the assumption of macro economy recovery throughout the entire forecast period. Worldwide semiconductor market is forecasted to be up 3.3 percent to $336 billion in 2015. For 2016, the market is forecasted to be $350 billion, up 4.3 percent.
By end market, automotive and communications (especially wireless) are expected to grow stronger than the total market, whereas consumer and computer are assumed to rermain almost flat.
By region, Asia-Pacific will be the fastest growing region and expected to reach $207 billion in 2016, which is almost 60 percent share of the total semiconductor market.
All major product categories will show a high single digit growth rate, except microprocessors which will show a soft decline. The growth will be largely driven by smartphones, tablets and automotive.
The highest growth rates are shown for the Analog (9.1 percent) and Sensor (9.1 percent) category. By region, all regions except Japan will grow from 2013. Japan market is forecasted to decline from 2013 in US dollar basis due to JPY depreciation compared to 2013.
Solid growth for all product categories is expected to continue over the next two years, under the assumption of macro economy recovery throughout the entire forecast period. Worldwide semiconductor market is forecasted to be up 3.3 percent to $336 billion in 2015. For 2016, the market is forecasted to be $350 billion, up 4.3 percent.
By end market, automotive and communications (especially wireless) are expected to grow stronger than the total market, whereas consumer and computer are assumed to rermain almost flat.
By region, Asia-Pacific will be the fastest growing region and expected to reach $207 billion in 2016, which is almost 60 percent share of the total semiconductor market.
Friday, October 24, 2014
Lucintel estimates that Asia Pacific will consume more than 35 percent of bulk molding compounds market by 2019
IRVING, USA: Bulk molding compounds (BMC) are used in a variety of markets, such as transportation, electrical & electronics, and consumer goods.
Bulk molding compounds have excellent flow characteristics, dielectric properties, and flame resistance which make them well-suited to a wide variety of applications, requiring precision in detail and dimensions as well as high performance.
Bulk molding compounds are ideal for headlamps, circuit breakers, housings, and valve covers due to their lightweight and higher thermal resistance properties. The Asia Pacific region is expected to represent more than 35 percent of the global bulk molding compounds market by 2019.
Bulk molding compounds (BMC) are expected to grow at a CAGR of 6.8 percent during 2014-2019. Electrical & electronics will remain the largest end user industry. Citadel Plastics, IDI Composites, Polynt, Premix, and Showa Denko are some of the suppliers of BMC materials for various applications. These companies are the important players in the BMC materials market because of their innovation and investment in research and development to find new applications.
Bulk molding compounds have excellent flow characteristics, dielectric properties, and flame resistance which make them well-suited to a wide variety of applications, requiring precision in detail and dimensions as well as high performance.
Bulk molding compounds are ideal for headlamps, circuit breakers, housings, and valve covers due to their lightweight and higher thermal resistance properties. The Asia Pacific region is expected to represent more than 35 percent of the global bulk molding compounds market by 2019.
Bulk molding compounds (BMC) are expected to grow at a CAGR of 6.8 percent during 2014-2019. Electrical & electronics will remain the largest end user industry. Citadel Plastics, IDI Composites, Polynt, Premix, and Showa Denko are some of the suppliers of BMC materials for various applications. These companies are the important players in the BMC materials market because of their innovation and investment in research and development to find new applications.
Thursday, October 23, 2014
Apple and Samsung drive adoption of next-generation sensors
EL SEGUNDO, USA: Propelled by the race between Apple and Samsung to enhance their mobile products with cutting-edge sensor technology, the market for sensors in cellphones and tablets is set to nearly triple from 2012 through 2018, according to IHS Technology.
Worldwide market revenue for sensors used in mobile handsets and media tablets will rise to $6.5 billion in 2018, up from $2.3 billion in 2012. The fastest-expanding portion of the mobile sensor segment will be emerging devices, whose revenue will surge to $2.3 billion in 2018, up from just $24 million in 2012. In 2013, this segment posted dramatic growth, with revenue rising to more than $500 million.
“The next wave of sensor technology in smartphones and tablets has arrived,” said Marwan Boustany, IHS senior analyst for microelectromechanical systems (MEMS) and sensors.
“Led by Apple and Samsung, the mobile market is moving beyond simply integrating established devices like motion sensors and now is including next-generation features like fingerprint and environment/health sensors. Adoption of these newer devices will drive the expansion of the mobile sensor device market in the coming years.”
Established sensors in mobile devices include motion sensors, light sensors and MEMS microphones. Emerging sensors consist of new devices including fingerprint, optical pulse, humidity, gas, ultraviolet (UV) and thermal imaging.
Information in this media release is contained in the new IHS Technology report entitled Emerging Sensors in Handsets & Tablets Report – 2014 from the Semiconductors & Components service.
Heightened sensors
Apple initiated the market for fingerprint sensors in mobile devices with the release of the iPhone 5s in 2013.
“Fingerprint sensors have arrived in force. IHS forecasts that shipments of fingerprint-enabled devices will reach 1.4 billion units in 2020,” Boustany said. “This is more than four times the 317 million units expected to be shipped by the end of 2014.”
The fingerprint sensor market is beginning to gain traction at other companies outside of Apple. New devices with fingerprint sensors include Samsung’s flagship model—the Galaxy S5—and Huawei’s top-of-the-line smartphone, the Ascend Mate 7, both of which began shipping in 2014.
For its part, Samsung has pioneered the deployment of other devices, including environmental and health sensors in the flagship models introduced by the company during the last 18 months. Samsung rolled out a humidity sensor in the Galaxy S4, a pulse sensor in the Galaxy S5 and a UV sensor in the Note 4.
Asian sensation
Fingerprint sensors play a key role in mobile payment services, providing authentication for systems like Apple Pay. Other banks and financial institutions, including Visa, MasterCard and PayPal are also working to support mobile payments and biometric authentication.
“This fingerprint market has all its requirements for success converging at the right time,” Boustany said.
Mobile payment services are expected to gain popularity not just in Europe and North America, but also in Asia.
With the increasing demand for sensor technology in Asia, IHS expects Chinese smartphone original equipment manufacturers (OEM) to be the next driver for a new generation of sensors.
Humidity sensors have been used in Chinese handsets since 2011. In the future, air-quality sensors will experience growing usage in China.
The first gas sensors have just been designed in by Chinese smartphone OEMs. IHS expects these phones will enter the market during the first half of 2015. There is also a specific demand for sensors that can detect particle pollution in large Chinese cities such as Beijing or Shanghai.
Extrasensory perception
In terms of revenue, fingerprint sensors now dominate the mobile market, followed by optical pulse sensors, humidity and UV sensors. IHS anticipates gas sensors will join the fray in 2015 and thermal imagers will arrive during the 2018 time period.
Thermal imagers using microbolometer sensors emerged from the technology of forward-looking infrared (FLIR) systems in 2014 as accessories for the iPhone 5s. However, it will take a few more years before these sensors decline enough in pricing to be embedded in smartphones.
IHS predicts that Samsung will adopt gas/chemical sensors in the Note 6 that will be introduced in 2016. This is because gas/chemical sensor technology will have matured and use cases will be more clearly defined by then.
Some sensors that have appeared in smartphones are likely to migrate to wearables, which in some cases are better platforms for health or environmental sensors.
Worldwide market revenue for sensors used in mobile handsets and media tablets will rise to $6.5 billion in 2018, up from $2.3 billion in 2012. The fastest-expanding portion of the mobile sensor segment will be emerging devices, whose revenue will surge to $2.3 billion in 2018, up from just $24 million in 2012. In 2013, this segment posted dramatic growth, with revenue rising to more than $500 million.
“The next wave of sensor technology in smartphones and tablets has arrived,” said Marwan Boustany, IHS senior analyst for microelectromechanical systems (MEMS) and sensors.
“Led by Apple and Samsung, the mobile market is moving beyond simply integrating established devices like motion sensors and now is including next-generation features like fingerprint and environment/health sensors. Adoption of these newer devices will drive the expansion of the mobile sensor device market in the coming years.”
Established sensors in mobile devices include motion sensors, light sensors and MEMS microphones. Emerging sensors consist of new devices including fingerprint, optical pulse, humidity, gas, ultraviolet (UV) and thermal imaging.
Information in this media release is contained in the new IHS Technology report entitled Emerging Sensors in Handsets & Tablets Report – 2014 from the Semiconductors & Components service.
Heightened sensors
Apple initiated the market for fingerprint sensors in mobile devices with the release of the iPhone 5s in 2013.
“Fingerprint sensors have arrived in force. IHS forecasts that shipments of fingerprint-enabled devices will reach 1.4 billion units in 2020,” Boustany said. “This is more than four times the 317 million units expected to be shipped by the end of 2014.”
The fingerprint sensor market is beginning to gain traction at other companies outside of Apple. New devices with fingerprint sensors include Samsung’s flagship model—the Galaxy S5—and Huawei’s top-of-the-line smartphone, the Ascend Mate 7, both of which began shipping in 2014.
For its part, Samsung has pioneered the deployment of other devices, including environmental and health sensors in the flagship models introduced by the company during the last 18 months. Samsung rolled out a humidity sensor in the Galaxy S4, a pulse sensor in the Galaxy S5 and a UV sensor in the Note 4.
Asian sensation
Fingerprint sensors play a key role in mobile payment services, providing authentication for systems like Apple Pay. Other banks and financial institutions, including Visa, MasterCard and PayPal are also working to support mobile payments and biometric authentication.
“This fingerprint market has all its requirements for success converging at the right time,” Boustany said.
Mobile payment services are expected to gain popularity not just in Europe and North America, but also in Asia.
With the increasing demand for sensor technology in Asia, IHS expects Chinese smartphone original equipment manufacturers (OEM) to be the next driver for a new generation of sensors.
Humidity sensors have been used in Chinese handsets since 2011. In the future, air-quality sensors will experience growing usage in China.
The first gas sensors have just been designed in by Chinese smartphone OEMs. IHS expects these phones will enter the market during the first half of 2015. There is also a specific demand for sensors that can detect particle pollution in large Chinese cities such as Beijing or Shanghai.
Extrasensory perception
In terms of revenue, fingerprint sensors now dominate the mobile market, followed by optical pulse sensors, humidity and UV sensors. IHS anticipates gas sensors will join the fray in 2015 and thermal imagers will arrive during the 2018 time period.
Thermal imagers using microbolometer sensors emerged from the technology of forward-looking infrared (FLIR) systems in 2014 as accessories for the iPhone 5s. However, it will take a few more years before these sensors decline enough in pricing to be embedded in smartphones.
IHS predicts that Samsung will adopt gas/chemical sensors in the Note 6 that will be introduced in 2016. This is because gas/chemical sensor technology will have matured and use cases will be more clearly defined by then.
Some sensors that have appeared in smartphones are likely to migrate to wearables, which in some cases are better platforms for health or environmental sensors.
Cadence announces broad portfolio of 3D memory verification IP
SAN JOSE, USA: Cadence Design Systems Inc. announced the immediate availability of verification IP (VIP) supporting all popular 3D memory standards including Wide I/O 2, Hybrid Memory Cube (HMC), High Bandwidth Memory (HBM) and DDR4 3D Stacking (DDR4-3DS).
The portfolio of memory VIP enables designers to accelerate the verification of memory interfaces and achieve earlier system-on-chip (SoC) verification closure for compute server applications, mobile devices, high-performance graphics and network applications.
Advanced features of these new VIP models include direct memory access for read, write, save, preload and comparison of memory contents, robust assertions, error configurability, transaction callbacks, assertion reports and a built-in address manager.
Additionally, the models support all leading third party simulators, verification languages and methodologies, enabling SoC verification teams with the fastest path to verify the correctness of interfaces to these new, specialized memories.
"Memory is a critical factor in increasing functionality and performance of advanced system topologies," said Robert Feurle, VP of compute and networking marketing at Micron. "The fact that Cadence is involved in the development of all the latest standards enables our designers to accelerate their adoption of innovative technologies such as Hybrid Memory Cube."
"3D memories are increasingly becoming essential to the next generation of electronic products," said Erik Panu, VP, Research & Development of the IP Group at Cadence. "The availability of Cadence VIP products supporting the latest standards facilitates a quick and convenient means for our customers to rapidly deploy the new 3D memory standards and to verify the correctness of their usage with SoC designs."
The portfolio of memory VIP enables designers to accelerate the verification of memory interfaces and achieve earlier system-on-chip (SoC) verification closure for compute server applications, mobile devices, high-performance graphics and network applications.
Advanced features of these new VIP models include direct memory access for read, write, save, preload and comparison of memory contents, robust assertions, error configurability, transaction callbacks, assertion reports and a built-in address manager.
Additionally, the models support all leading third party simulators, verification languages and methodologies, enabling SoC verification teams with the fastest path to verify the correctness of interfaces to these new, specialized memories.
"Memory is a critical factor in increasing functionality and performance of advanced system topologies," said Robert Feurle, VP of compute and networking marketing at Micron. "The fact that Cadence is involved in the development of all the latest standards enables our designers to accelerate their adoption of innovative technologies such as Hybrid Memory Cube."
"3D memories are increasingly becoming essential to the next generation of electronic products," said Erik Panu, VP, Research & Development of the IP Group at Cadence. "The availability of Cadence VIP products supporting the latest standards facilitates a quick and convenient means for our customers to rapidly deploy the new 3D memory standards and to verify the correctness of their usage with SoC designs."
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