Mentor Graphics announces FloEFD targeting new apps and localized GUIs

WILSONVILLE, USA: Mentor Graphics Corp. has announced the next generation of the FloEFDTM concurrent computational fluid dynamics (CFD) simulation product addressing a broader range of real-world challenges such as radiation, combustion and hypersonic flows.

Its intuitive user interface is now available in the most popular languages in the engineering world such as German, French, Japanese and Chinese, thereby increasing engineering efficiency because users will be able to work in their native language. With unparalleled ease-of-use, the FloEFD product empowers mechanical engineers who may not be experts in general fluid dynamics or thermal simulation to effectively conduct such analyses and to create better products faster.

Bronswerk Heat Transfer BV, based in Nijkerk, Netherlands, is a manufacturer of market-leading and innovative heat transfer and fluid flow systems for the energy and process industries. Their engineering team developed a new generation of efficient air-cooled cooling systems that are superior to other products on the market.

“We chose FloEFD, a proven Concurrent CFD toolset for analysis and validation of our Whiz-wheel fan,” said Guus Bertels, associate director of advanced design and analysis at Bronswerk. “Over the past few years we have used both CFD tools and physical measurements to characterize the behavior, particularly the aerodynamics, of large air-cooled cooling systems. We have learned that Concurrent CFD often can produce data that would be impossible to acquire with measurements, due to physical constraints, the Heisenberg principle, and other factors, therefore, we have been able to produce a truly revolutionary design. Our Whizz-wheel based cooling systems are breaking all industry records for energy efficiency, nose reduction and weight savings.”

“Our latest version of FloEFD concurrent CFD addresses the key challenges our customers require by providing advanced simulation and analyses,” said Erich Buergel, GM of Mentor Graphics Mechanical Analysis Division. “Our easy-to-use yet powerful multiCAD-embedded CFD solution provides straightforward simulations that help users at all technical levels to quickly identify design problems and improve product quality.”

The FloEFD product is available with two new optional modules, providing the following features for improved productivity and efficiency:

FloEFD with “Advanced Module” for combustion and hypersonic flows: The FloEFD tool can simulate combustion of gas-phase mixtures (fuel and oxidizer) using the equilibrium approach. To effectively analyze such cases, the equilibrium model is extended for pre-mixed combustion at the onset and upon mixing gases. Also the FloEFD product can now analyze physical changes in airflow such as molecular dissociation and ionization.

FloEFD with “HVAC module” for radiation flow and comfort parameters: Advanced radiation model for semi-transparent layers: This feature supports previous customer requests for automotive and HVAC applications by extending the radiation models to semi-transparent solid materials such as glass and plexiglass. Applications where this feature is valuable include space heaters, automotive lighting, commercial lighting devices, glass walls and windows in structures.

Comfort parameters for thermal efficiency and ventilation: The following comfort parameters can be measured with the FloEFD product: predicted mean vote, draft temperature, predicted per cent dissatisfied, flow angle, and local air quality index for fluids.

The new modules are available for all FloEFD products, including the FloEFD product for ProENGINEER and Creo Elements/Pro, the FloEFD product for CATIA V5, and the FloEFD for NX product.

Concurrent CFD for advanced productivity and reliability
The Mentor Graphics Concurrent CFD methodology can reduce simulation time by as much as 65 to 75 percent compared to traditional CFD tools. It enables users to optimize product performance and reliability while reducing physical prototyping and development costs without time or cost penalties. The FloEFD product is an established technology and supported by a dedicated CFD development team.

Mentor Graphics is the world’s third largest general purpose CFD provider with the largest knowledge base in electronics cooling.

Analog Devices’ MEMS accelerometers help precision archers hit their targets

NORWOOD, USA: Analog Devices Inc. (ADI) is providing its award-winning iMEMS technology to a first-of-its kind measurement system used in high-precision archery.

ADI’s ADXL346 3-axis digital MEMS (micro-electromechanical systems) accelerometer was selected by Full Flight Technology for use in the company’s flagship Velocitip Ballistic System, which is the first ever to use an arrow-mounted device to provide detailed information about arrow speed, flight dynamics and bow performance. Full Flight Technology is a leading innovator and developer of world class technology for ballistic measurement located in Cambridge, Massachusetts.

Designed for archery equipment manufacturers, sportsmen and competitive archers, the Velocitip Ballistic System includes a field point (arrow tip), battery pack, docking station, USB cable and PC software. The system employs the ADXL346 to continuously measure arrow drag in flight to provide downrange performance data. The ability to measure arrow drag means that, unlike a ballistic chronograph, the system does not require down-range equipment to measure arrow performance at target impact. The archer simply threads the arrow tip to the arrow in a conventional manner and shoots at the target.

“The functionality combined with a simple user interface make the Velocitip System a great tool for anyone testing archery equipment performance,” said Nick Meinert, engineering and technical support, Victory Archery, which designs and manufactures carbon-fiber arrows. “Because so much useful information is precisely recorded for each shot, we find that the Velocitip System enables us to more quickly and easily identify those factors most important to improving arrow design and downrange performance.”

“This is without a doubt the most sophisticated microelectronics technology ever applied to the field of archery,” said Bob Donahoe, founder of Full Flight Technology. “ADI’s ADXL346 accelerometer is an essential enabling technology for our Velocitip Ballistic System thanks to its ability to survive repeated hi-g shock, its small package, and the perfect combination of precision measurement, low power, rugged construction and light weight.”

With today’s modern archery equipment, an arrow experiences over 1,000 g at launch and over 4,000 g at impact, for each shot. Each tip must be able to survive for a minimum of 100 shots. During product development, the ADXL346 was housed in an arrow tip and successfully tested for 100 cycles at 5,000 g. The ADXL346 MEMS accelerometer is housed in a 9-mm-diameter aluminum arrow tip and weighs less than 6.5 grams. Coin cell batteries power the arrow tip for a minimum of 100 shots. Providing high 13-bit resolution measurement at up to ±16 g, the ADXL346 also features an integrated memory-management system with a 32-level FIFO (first-in, first-out) buffer to store ballistics data.

DMAP announces DO-254 DAL semiconductor IP, fully verified with Mentor Graphics Questa functional verification platform

TOULOUSE, FRANCE: DMAP, a company focused on high reliability semiconductor applications and producing DO-254 compliant IP, has made available to the market PCI Express and Ethernet (Gigabit, 10G) IP for DO-254 applications that has been verified using SystemVerilog and Assertion Based Verification (ABV) in an OVM environment.
Adherence to DO-254 compliance during development, and verified using advanced verification methods supported by Mentor Graphics industry-leading Questa functional verification platform, ensures thorough testing of these complex IP devices.

DO-254 explicitly requires functional coverage, a verification approach that ensures all requirements have been covered in the designed hardware. The DO-254 standard states the following: “Evidence is provided that the hardware implementation meets the requirements” [DO-254 6.2.1-1]. Regardless of the level of design (LRU, board, device, IP) and design assurance level (DAL) of the item, functional coverage is the fundamental metric of every ‘safe’ design flow.

Supplementing a requirements-driven approach to verification and functional coverage, HDL code coverage is also commonly used in DO-254 programs. While not explicitly mentioned in DO-254, code coverage is often used in support of elemental analysis, an advanced verification method described in DO-254 Appendix B to ensure that all the design elements have been exercised during verification. Newer regulatory policy has mandated the use of code coverage for DAL A and B digital hardware projects.

Specifically, the recent EASA CEH memo states”…an HDL code coverage measurement is an acceptable means to assess the way the HDL code has been exercised during device functional verification by simulation.” [EASA CM-SWCEH-001 8.4.2.1]. With Questa functional verification platform from Mentor Graphics, DMAP’s verification team has been able to reach 100 percent coverage on both hardware requirements (i.e., functional coverage) and HDL code (i.e., code coverage) in an automated way.

Quite straightforward, both functional and code goals are extracted from the document, which describes the verification procedures (HVCP) or verification‘s code (SV) then Questa simulator is able to automatically answer the question: Are we done?

“DMAP’s team is pioneering advanced verification techniques on DO-254 compliant IP” stated Michelle Lange, DO-254 program manager at Mentor Graphics. “It’s good to see these methods – which are used extensively in every other industry because they offer more efficient and higher quality results – being used now in an industry where the verification effectiveness is so crucial. DMAP, with their use of Questa and advanced methods, is demonstrating their leadership and understanding of the value of these methods in support of safety-critical design.”

“By using more modern verification techniques such as SystemVerilog, formal methods, ABV, and Bus Functional Models (BFMs), we are now able to reach all DO-254 goals on very high complex IP or FPGA designs in a short amount time and for a competitive cost,” said James Bezamat, CEO and DO-254 evangelist at DMAP.

Already available for DO-254 DAL A designs, our Generation One PCI Express Endpoint and 10/100/100 Ethernet MAC semiconductor IP products can be customized on request to match your needs. The DMAP’s product list also includes ARINC429 and CAN bus interface.

Microchip integrates sub-GHz wireless transmitter with 8-bit PIC MCU to simplify secure remote keyless entry designs

CHANDLER, USA: Microchip Technology Inc. announced the PIC12LF1840T48A—the first in a family of single-chip devices that integrate an eXtreme Low Power (XLP), 8-bit PIC microcontroller with a sub-GHz RF transmitter.

The PIC12LF1840T48A’s combination of features in a single, 14-pin TSSOP package makes it ideal for space-, power- and cost-constrained applications, such as remote keyless entry fobs for automobiles, garage doors and home security systems, as well as a broad range of other home and building automation systems. Additionally, the device is optimized to run Microchip’s royalty-free KEELOQ® advanced code-hopping technology, a proven security technology used worldwide by leading manufacturers.

In addition to being optimized for secure wireless communication, the PIC12LF1840T48A is designed to maximize battery life via an extremely low operating voltage of 1.8V. Furthermore, the XLP microcontroller has extremely low sleep current consumption, and is efficiently integrated with the transmitter to enable fast wake-up and send functionality that takes full advantage of the MCU’s 8 MIPS operation.

“Microchip has built on our knowledge and experience in security and authentication to provide a new level of integrated performance and low power consumption,” said Steve Caldwell, director of Microchip’s Wireless Products Division. “By combining our XLP PIC12LF1840 microcontroller with a highly efficient sub-GHz RF transmitter, we are now able to provide a complete single-chip remote control solution with KEELOQ security capabilities.”

VeriSilicon licenses wide range of ARM technology for advanced consumer and embedded apps

SANTA CLARA, USA & CAMBRIDGE, UK: ARM and VeriSilicon Holdings Co. Ltd announced that VeriSilicon has licensed a wide range of ARM Intellectual Property (IP). This includes selected cores from the high performance, energy-efficient ARM Cortex processor and ARM Mali GPU families, and ARM Artisan Physical IP.

Access to this broad range of ARM IP will enable VeriSilicon to provide its highly differentiated, platform-based system-on-chip (SoC) design and turn-key services. In particular VeriSilicon’s ‘specification to chip’ (‘spec to chip’) services will support customers in key markets, such as mobile computing, smart-TVs, cloud computing and ’Internet of things’.

Leveraging the latest ARM IP in its SoC platforms, VeriSilicon is able to reduce costs and time to market for customers, whilst ensuring high quality SoC solutions. The agreement includes VeriSilicon licenses for the Cortex-A9 MPCore (with Artisan Processor Optimization Packs [POPs]), Cortex-A8 and Cortex-A5 processors, and ARM Mali-400 MP GPU. Additionally Cortex-R4, Cortex-M0 and Cortex-M3 processors for use in embedded applications have also been licensed.

"Our customers demand high quality custom silicon solutions delivered in a timely and cost-effective manner," commented Dr. Wayne Dai, president and CEO, VeriSilicon. “This agreement provides VeriSilicon’s customers with access to a rich portfolio of ARM IP. Our SoC platforms and world class design capabilities allow us to unleash the performance potential and energy-efficiency of the ARM processors we have licensed. This provides differentiated custom silicon solutions for a range of consumer markets.”

As an ARM Partner, VeriSilicon is part of the ARM Connected Community, a global network of over 900 companies with access to a wide variety of resources and aligned to provide optimized solutions based on the ARM architecture. VeriSilicon recently opened one such resource: the first certified ARM Design Center in China.

“Consumers are demanding an increasingly connected life and suppliers of advanced semiconductor solutions must address this requirement for smarter devices,” said Tudor Brown, president, ARM. “The new agreement with VeriSilicon will allow their customers to address these consumer demands, and benefit from the ARM architecture and our latest IP. We look forward to working with VeriSilicon as part of the wider ARM ecosystem, and are excited about the potential value of its platform-based ‘spec to chip’ design and turn-key services.”

2H’Nov. contract price dipped almost 8 percent; 2GB contract price plunged below $10

TAIWAN: According to DRAMeXchange, a research division of TrendForce, due to the PC slow season and the HDD supply chain afflicted by the Thailand flood, the downtrend of the contract price persisted in 2H'11: the ASP of DDR3 4GB dropped by 7.9 percent to $17.5, while DDR3 2GB ASP plunged below $10 to $9.5, a 7.3 percent decline.

From the market perspective, due to the weak demand for PC in November – some PC OEMs' orders were even cancelled –, the market remained slow. Affected by the inventory pressure, several DRAM manufacturers resorted to cutting prices. In addition, the DDR3 2GB spot price dipped 25 percent compared to last month, which gave the clients an edge in the contract price negotiation and in turn furthered the price drop.

Although DRAM makers such as Elpida and Nanya downsized their capacities in November, the effect of downsizing will not kick in until 1Q12. In the short term, the DRAM market will still be in a state of oversupply, with the contract price downturn most likely to continue through the end of 2011.

Round two of DRAM production cut to spur industry consolidation and end price downtrend in 2H'12
The contract price of DDR3 2GB dropped from $18.75 in May 2011 to the current ASP of $9.5, a 50 percent decrease; the spot price of DDR3 2GB plunged by 70 percent to $0.74. With price falling below the cash costs of many DRAM makers, companies with weaker financial health have downsized their capacities or shifted their focuses to other sectors.

On account of its unbalanced financial condition, ProMOS was the first company to downsize the wafer start volume, which was reduced from 50K level in July to about 5K at present. As for PSC, due to the decreased orders from Elpida and the company’s increasing focus on OEM business and Flash products, the wafer start volume of PSC’s standard DRAM was reduced from 80K per month to about 20-30K.

In light of the persisting DRAM price downtrend in 2H’Oct, more DRAM makers have downsized their capacities in November: Nanya not only downsized its mother plant’s wafer start volume by 20% but also reduced its wafer start volume in Inotera. Moreover, Nanya also endeavors to strengthen its consumer DRAM business in the hope of reducing its loss. The Hiroshima plant of Elpida, the first global major manufacturer to announce cutting utilization rate, is scheduled to reduce the capacity by 25 percent. Rexchip will decide whether or not to downsize in December.

According to TrendForce’s survey, due to the production cut in November, the global DRAM industry’s wafer start volume fell from 1300K per month to approximately 1100K, representing a 16 percent downturn. Considering the DRAM manufacturers’ active attitude towards the 30nm and 20nm process migration and the PC slow season in 1H12, DRAM is expected to continue facing a serious oversupply.

Currently, the decrease on wafer start will help stabilize the price, but a balanced supply and demand hinges upon whether the global brands, including Samsung and Hynix, will join the ranks of downsizing and whether Ultrabook and Windows 8 will spur the demand in 2012. If not, the continuous production cut may trigger DRAM companies to merge, resulting in an oligopoly market.

In this case, the industry will be depending on the market mechanism to weed out the weak and aid the DRAM price to rebound gradually in 2H12.

LatticeECP4 family redefines low cost, low power FPGAs

BANGALORE, INDIA: Lattice Semiconductor Corp. has redefined the low cost, low power mid-range FPGA market with its announcement of the next generation LatticeECP4 FPGA family, with 6 Gbps SERDES in low cost wire-bond packages, powerful DSP Blocks and hard IP-based Communication Engines for cost- and power-sensitive wireless, wireline, video, and computing markets.

The LatticeECP4 FPGA family builds on the award winning LatticeECP3 family by bringing premium features to mainstream customers while maintaining industry-leading low power and low cost. The LatticeECP4 devices are ideal for developing mainstream platforms for a variety of applications such as Remote Wireless Radio Heads, Distributed Antenna Systems, Cellular Basestations, Ethernet Aggregation, Switching, Routing, Industrial Networking, Video Signal Processing, Video Transmission and Data Center Computing.

High quality SERDES and hardened communication engines
The LatticeECP4 FPGAs contain up to 16 CEI-compliant 6 Gbps SERDES channels with embedded Physical Coding Sub-layer (PCS) blocks in both low cost wire-bonded and high performance flip chip packages, giving customers the choice to deploy the LatticeECP4 FPGA in chip to chip as well as long haul backplane applications.

The versatile and configurable SERDES/PCS can be seamlessly integrated with the hardened Communication Engines to economically build complete high bandwidth sub-systems. The Communication Engines offer up to 10X the power and cost reduction of similar implementations in FPGA fabrics. The LatticeECP4 Communication Engines portfolio includes solutions for PCI Express 2.1, multiple 10 Gigabit Ethernet MAC and Tri-speed Ethernet MACs as well as Serial Rapid I/O (SRIO) 2.1. The combination of SERDES/PCS and Communication Engines is ideal for completing complex serial protocol-based designs with lower cost, power and footprint while accelerating time to market.

Innovative DSP processing reduces multiplier count
The LatticeECP4 family features powerful digital signal processing (DSP) blocks with 18x18 multipliers, wide ALUs, adder-trees and carry chains for cascadability. Unique booster logic means each LatticeECP4 DSP block can be equal to four LatticeECP3 DSP blocks, enabling up to 4X the signal processing capability of the previous generation LatticeECP3 devices. The flexible 18x18 multipliers can be split into 9x9 or combined into 36x36 to perfectly match customers’ application requirements. Moreover, up to 576 multipliers can be cascaded together to build complex filters for wireless Remote Radio Heads (RRH), MIMO-based RF antenna solutions and video processing applications.

Higher performance and capacity
The LatticeECP4 FPGAs are up to 50 percent faster than previous generation devices and feature 1066 Mbps DDR3 memory interfaces and 1.25 Gbps LVDS I/Os that are also capable of being provisioned as serial Gigabit Ethernet interfaces. LatticeECP4family also has 66 percent more logic resources and 42 percent more embedded memory to empower design engineers to construct complete systems-on-chip in FPGAs.

"The next generation LatticeECP4 FPGA family offers our customers an unprecedented combination of the premium features, high performance, low cost and low power that is necessary for sophisticated but cost sensitive wireless, wireline, video and computing applications. Lattice has been a pioneer in providing cutting-edge innovations in economical devices for our customers. With the LatticeECP4 devices now included in our Lattice Diamond design software, our customers can begin immediately to build broad-based, lower power platforms to expand their markets,” said Sean Riley, Lattice corporate VP and GM, Business Group.

Design support for LatticeECP4 FPGAs
Lattice provides intellectual property (IP) cores, development boards and design software for quick launch of design initiatives and rapid time to market. A range of intellectual property (IP) cores will include CPRI, OBSAI, Serial RapidIO, XAUI, SGMII/Gigabit Ethernet, PCI Express, SMPTE for serial connectivity, FIR filters, FFT, Reed-Solomon encoders/decoders, CORDIC, CIC, NCO for DSP functions and several others for memory interfaces and connectivity.

Lattice Diamond design environment accelerates development time
Customers can begin designing with LatticeECP4 FPGAs now using the Lattice Diamond 1.4 beta design software. Lattice Diamond design software is the new flagship design environment for Lattice FPGA products and provides a complete set of powerful tools, efficient design flows and a user interface that enables designers to more quickly target low power, cost sensitive FPGA applications.

In addition, Lattice Diamond software continues to provide industry-leading features specifically developed for low cost and low power applications. These include a very accurate power calculator, pin-based simultaneous switching output noise calculator and proven MAP and PAR FPGA implementation algorithms that help ensure low cost and low power design solutions. To learn more about the Lattice Diamond Design Environment, please visit: www.latticesemi.com/latticediamond.

LatticeECP4 FPGA family
The LatticeECP4 FPGA family is comprised of six devices that offer standards-compliant multi-protocol 6G SERDES in low cost wire-bond packages, DDR1/2/3 memory interfaces with speeds up to 1066 Mbps, and powerful, cascadable DSP blocks that are ideal for high performance RF, baseband and image signal processing.

Toggling at 1.25 Gbps, the LatticeECP4 FPGAs also feature fast LVDS I/O as well as embedded memory of up to 10.6 Mbits. Logic density varies from 30K LUTs to 250K LUTs with up to 512 user I/O. The LatticeECP4 FPGA family's high performance features include:

* DSP blocks that allow up to 36x36 Multiply and Accumulate functions running at >500MHz. The DSP slices also feature innovative cascadability for implementing wide ALU and adder tree functions without the performance bottlenecks of FPGA logic. The DSP block offers booster logic, which allows 4X the bandwidth per DSP block relative to previous generation DSP architectures

* 6 Gbps SERDES CEI-6G jitter compliance and the ability to mix and match multiple protocols on each SERDES quad. This includes PCI Express 2.1, CPRI, OBSAI, XAUI, Serial RapidIO 2.0, SGMII/Gigabit Ethernet and 10 Gigabit Ethernet.

* The SERDES/PCS blocks have been designed specifically to enable the design of the low latency variation CPRI links that are found in wireless basestations with Remote Radio Head connectivity.

* Hardened Communication Engine blocks using hardened metal arrays featuring multiple 10GbE and Triple Speed MAC blocks, as well as PCI Express 2.1 and SRIO 2.1 blocks. These blocks are 10X more area- and power- efficient that traditional FPGA-based implementations.

* Compliance to the SMPTE Serial Digital Interface standard, with the unprecedented ability to support 3G, HD and SD video broadcast signals independently on each SERDES channel. The triple rate support is performed without any oversampling technique, consuming the least possible amount of power.

* 1.25 Gbps LVDS I/O, with Clock Data Recovery blocks, allows interfacing to high performance ADCs/DACs and implementation of SGMII/GbE links. The ability to perform CDR functionality on general purpose I/O greatly increases the number of serial I/O available to the designer, allowing smaller FPGAs to be used even when a large number of SERDES channels are needed, greatly reducing the cost of implementing serial Ethernet interface logic.

These features make the LatticeECP4 FPGA family ideally suited for deployment in high volume cost- and power-sensitive wireless infrastructure, wireline access equipment, video and imaging, as well as computing applications.

Select customers are already designing with LatticeECP4 FPGAs using the Lattice Diamond 1.4 beta design software. Device samples will be available in the first half of 2012 and high-volume production delivery is scheduled for the second half of 2012.

ARM launches free toolkit for Android app developer community

CAMBRIDGE, UK: ARM announced the release of the ARM Development Studio 5 (DS-5) Community Edition (CE) – a free-to-use edition of its reference software development toolkit.

The new edition is dedicated to the Android application developer community and helps them create native software for compute intensive tasks that can run up to 4 times faster than Java code. DS-5 CE complements the standard SDK and NDK Android development kits by offering developers a unique set of tools to help them achieve the performance and energy-efficiency advantages made possible when ARM native code is used in Android applications.

DS-5 Community Edition includes limited, but essential functionality from the premium DS-5 toolkit to help solve common Android application developer pain points. It achieves this by providing an integrated graphical debugger for NDK-generated code and visibility of advanced processor information, including ARM NEON Single Instruction Multiple Data (SIMD) registers. The new toolkit permits development of Java and C/C++ code in the same Eclipse integrated development environment (IDE) to maximise productivity and ease of use.

DS-5 Community Edition features a tailored version of the ARM Streamline Performance Analyzer for use with compatible Android development platforms. Streamline captures detailed, system-wide performance statistics from a variety of sources, which helps developers to locate hotspots in their code and isolate potential causes. Platform builders can add support for Streamline by integrating an open source driver available from the Linaro website.

“With over half a million apps on the Android market today, developers need to deliver an outstanding user experience to succeed commercially,” said John Cornish, executive VP and GM, system design division, ARM. “ARM DS-5 Community Edition offers developers an easy to use environment for debugging and optimizing C/C++ code. This allows them to take full advantage of ARM processor technology using native code to deliver the performance and functionality that consumers demand.”

Dialog power management and Audio ICs adopted by Samsung for Android smartphones

KIRCHHEIM & TECK, GERMANY: Dialog Semiconductor plc is shipping system level power management and low power audio ICs in a system-in-package (SIP) to Samsung for use in its S-5368 TD-SCDMA smartphone. The S-5368 is targeted at the Chinese market and will be distributed via China Mobile, the largest Chinese mobile phone operator.

Dialog’s success at Samsung can be largely attributed to it being the first company to combine a highly complex system power management IC that is fully configurable for multiple platforms, together with a low power class D audio codec IC that includes a digital signal processor in a single package. This enables significant power and board space savings, whilst delivering the highest quality audio for Samsung’s new smartphones.

Smartphones, with an annual growth of 44 percent in the last year, accounted for 26 percent of all handset sales during Q3 2011. Samsung shipped 28 million smartphones and was the world’s largest smartphone vendor by volume with 24 percent market share. Going forward, the Chinese market represents the largest opportunity for further mass proliferation of smartphones as the previously dominant ‘feature phones’ segment increasingly converts to lower cost smartphones.

Jalal Bagherli, CEO of Dialog said: “Samsung produces very attractive and elegant smartphones, integrating state-of-the-art features combined with the ability to achieve differentiation based on the Android operating system at attractive market price points, to produce some of the world’s most sought after handsets.

“This is a significant milestone for Dialog as we extend our leadership in power management ICs and high quality audio for smartphones. We now look forward to the global roll-out of additional models based on this platform in the coming months, which will also include smartphones for the very popular Galaxy S-II series.”

Measuring 107 × 60.5 × 11.9mm, the S-5368 is a fully featured smartphone, offering full touch phone capability and is based on the popular Android 2.3 operating system.

Samplify Systems announces availability of first ultrasound beamforming ASIC for merchant market

CHICAGO, USA: Samplify Systems Inc., a technology company focused on delivering innovative semiconductors, modules, and subsystem solutions to the ultrasound industry, has announced availability of the industry's first merchant beamforming ASIC—the SAM2032.

The highly integrated SAM2032 leverages all the benefits of Samplify's award-winning Autofocus technology in a receive beamforming ASIC offering the industry's lowest power consumption and highest performance compared to current FPGA-based beamformer implementations. The highly configurable ASIC provides the flexibility for ultrasound OEMs to simplifying software and system design thus speeding time to market for a wide range of machines from ultra-low power hand-helds, through mid-range and high-end carts.

The receive beamformer is at the heart of any ultrasound front-end electronics sub-system. The SAM2032 ASIC addresses a critical gap in the current FPGA implementation of these devices. While higher-end FPGAs can be used to develop a high-performance receive beamformer, their higher cost, higher power consumption, and larger size limits their use to premium console ultrasound machines. Conversely, lower-end FPGAs can be used as a cost-effective alternative, but their limited resources present system performance constraints.

"The availability of the SAM2032 is an exciting development in the ultrasound industry," says Danny Kreindler, director for Ultrasound Products at Samplify Systems. "By capturing all of the receive beamformer's complexity in an ASIC device, the SAM2032 delivers the only high-performance, low-power and low-cost solution in the commercial market. The availability of this ASIC enables existing and new entrants, in both the traditional OEM space and in emerging non-traditional ultrasound applications, to gain quick and easy access to premier beamforming technology that will significantly accelerate product development."

SAM2032 highlights
The SAM2032 is a configurable 32-channel digital receive beamformer. The device interfaces to 12-bit ADCs with 32 serialized LVDS inputs. The high-performance data-path consists of delay memory, cubic interpolation, and apodization weighting prior to summation of the 32 channels. The device supports dynamic focusing and apodization where coefficients are updated continuously on every sample. RF beam data is converted to baseband using a true I/Q down converter for optimal noise performance.

With a tunable center frequency and programmable decimation filter bandwidth, an optimal tracking filter throughout the entire scan depth can be implemented. The device supports sampling rates of up to 50MHz and parallel beam processing using Samplify's QuadBeam technology that generates up to 4 receive beams simultaneously for higher frame-rates for color overlays.

Samplify's on-board AutoFocus engine is an application specific DSP that calculates the coefficients and weights for the beamformer data-path in real-time. This calculator reduces system complexity and cost because no external memory or real-time link to the back-end CPU is required.

The SAM2032 comes in a 672-ball 27x27mm PBGA lead-free package. Based on imaging modes employed, the device consumes a fraction of the power of comparable FPGA implementations.

Renesas intros two single-channel industrial Ethernet PHY chips

TOKYO, JAPAN: Renesas Electronics Corp. has announced the availability of two single-channel Ethernet physical layer (PHY, part number μPD60610GA-GAM-AX and μPD60611GA-GAM-AX) devices for industrial communication systems.

The two new PHY chips expand Renesas’ family of PHY devices designed for industrial Ethernet requirements, which includes two dual-channel PHY devices (the μPD60620GA-GAM-AX and the μPD60621GA-GAX-AX).

Recently, there has been a growing demand among manufacturing companies for the intelligent field devices that can capture and transmit information within the factory. This requirement for more efficiency and transparency has accelerated the adoption of industrial Ethernet to interconnect industrial automation systems. The multiple differences between this environment and PC-based and consumer applications have provided the impetus for the development of new standards based on the IEEE802.3 standard.

Examples of these differences compared to consumer PHY devices include the need for determinism, real-time and diagnostics features, a high level of reliability, and an extended lifecycle. Renesas prioritised all of these capabilities when developing its new PHY family for industrial automation applications.

Android app for cultural participation adds new dimension to NFC

SINGAPORE: NXP Semiconductors N.V., together with start-up U-Approach, is providing visitors of the STRP Festival in Eindhoven – one of Europe’s largest art and technology festivals - the ability to use smartphones equipped with Near Field Communication (NFC) to interact with its cultural exhibits.

Using a new Android app, visitors can get detailed information about the exhibited artwork, simply by tapping an NFC-enabled smartphone over an NFC tag, triggering a synthesized voice message. The mobile app also allows people to ‘love’ an art work (with up to five ‘hearts’), tag it with a keyword, and share it via social media.

Works of art tapped during a visit can be converted into a personalized poster, combining collaboratively created visitor opinions. In this way, the Android app encourages cultural participation, enriches the festival experience, and introduces a new dimension to NFC.