HAUPPAUGE, USA: SMSC, a leading semiconductor company creating valued connectivity ecosystems, announced that its High Speed Interconnect (HSIC) USB4640, a USB 2.0 hub plus Flash Media Reader combo device is available now.
HSIC, which incorporates SMSC’s patented Inter-Chip Connectivity (ICC) technology, enables silicon devices, System in Package (SIP) solutions and Multi-Chip Modules (MCM) connected on a circuit board utilizing the ubiquitous USB 2.0 protocol. HSIC has been adopted as part of the USB 2.0 standard and dramatically decreases power consumption in applications such as battery-powered portable devices.
When connectivity between a host and a peripheral demands the use of a cable or a connector, the USB 2.0 standard is currently the de facto solution. However, the USB 2.0 interface requires the use of an analog Physical Layer interface (PHY) in order to transmit the signaling up to 5 meters over cabling.
When the application needs the same level of interoperability offered by the cabled version of USB 2.0, and the distance between the host or hub and the peripheral is 10 centimeters or less, and does not require the use of a connector, HSIC is the lowest cost and lowest power solution available today. The power reduction is most obvious when actively transferring data, and has been measured to be one seventh of the power consumed by a pair of traditional USB 2.0 PHYs.
With so many devices being introduced into the market that require ultra low power consumption, HSIC provides a “green” interface alternative that retains the benefits of being 100 percent compatible with the higher power traditional USB 2.0 interface.
“Using HSIC, which incorporates SMSC’s patented inter-chip connectivity technology, silicon designers can take advantage of the universal availability of software and systems support for USB 2.0 while enjoying the benefits of making the physical interconnect using a digital interface,” said Christine King, CEO of SMSC. “This reduces the size of the silicon while dramatically reducing the amount of power consumed on both ends of the connection.”
SMSC’s ICC technology is described in U.S. Patent No. 7,702,832, which was issued to SMSC on April 20, 2010. Additional related patent applications have been filed by SMSC in the United States and other countries. As provided for in the appropriate agreements, USB 2.0 promoters and companies that have timely signed both the USB 2.0 Adopters Agreement and a related HSIC amendment letter may license SMSC’s ICC technology patents under reasonable and non-discriminatory (RAND) terms.
Further, SMSC’s ICC technology is now available to the industry at large through individually-negotiated patent licenses from SMSC.
Tuesday, June 29, 2010
Global Semiconductor Alliance and VLSIresearch announce partnership
SAN JOSE, USA: The Global Semiconductor Alliance (GSA), the voice of the global semiconductor industry, and VLSIresearch (VLSI) today announced an alliance aimed at providing industry executives with timely and detailed market intelligence on the global semiconductor, foundry, and associated supplier markets.
GSA, well known for its wealth of market intelligence, offers industry executives information and tools to make better tactical and strategic business decisions for their companies. To further enhance its market intelligence resources, GSA strategically partners with leading organizations globally to improve its portfolio of relevant industry research products.
“Our mission is to continually provide value-added services to our membership to enhance visibility into the marketplace. Comprehensive and unique market intelligence is one important area than allows our members to keep abreast of the constantly evolving marketplace,” said GSA’s vice president, Lisa Tafoya. “Combining the GSA’s valuable market research capabilities with that of VLSI’s will give our worldwide members the ability to track and follow global markets trends as well as the ability to identify and articulate the landscape of market opportunities.”
Through this partnership, GSA will offer its members the use of VLSI’s The Chip Insider® and ForecastPro Modules. The modules contain electronic and macroeconomic data, semiconductor regional distribution, weekly indicator reports and more. Chip inventories, capacity utilization, electronics shipments, and even weekly sales activity in chips and electronics will be available as monthly statistics, providing essential information required for effective tactical agility.
“The companies which navigate the silicon cycle best are those with the most detailed and timely market intelligence,” said Mr. G. Dan Hutcheson, CEO of VLSIresearch. “Better information leads to better decisions and ultimately to better results. The combined market research capabilities of GSA and VLSI will provide significant intelligence on the marketplace. We are pleased to be working with GSA and believe our partnership will provide significant benefits to their membership worldwide.”
As part of initiating the partnership, VLSI will offer GSA members a complimentary live market update. These market updates will cover the current outlook and state of the industry.
GSA, well known for its wealth of market intelligence, offers industry executives information and tools to make better tactical and strategic business decisions for their companies. To further enhance its market intelligence resources, GSA strategically partners with leading organizations globally to improve its portfolio of relevant industry research products.
“Our mission is to continually provide value-added services to our membership to enhance visibility into the marketplace. Comprehensive and unique market intelligence is one important area than allows our members to keep abreast of the constantly evolving marketplace,” said GSA’s vice president, Lisa Tafoya. “Combining the GSA’s valuable market research capabilities with that of VLSI’s will give our worldwide members the ability to track and follow global markets trends as well as the ability to identify and articulate the landscape of market opportunities.”
Through this partnership, GSA will offer its members the use of VLSI’s The Chip Insider® and ForecastPro Modules. The modules contain electronic and macroeconomic data, semiconductor regional distribution, weekly indicator reports and more. Chip inventories, capacity utilization, electronics shipments, and even weekly sales activity in chips and electronics will be available as monthly statistics, providing essential information required for effective tactical agility.
“The companies which navigate the silicon cycle best are those with the most detailed and timely market intelligence,” said Mr. G. Dan Hutcheson, CEO of VLSIresearch. “Better information leads to better decisions and ultimately to better results. The combined market research capabilities of GSA and VLSI will provide significant intelligence on the marketplace. We are pleased to be working with GSA and believe our partnership will provide significant benefits to their membership worldwide.”
As part of initiating the partnership, VLSI will offer GSA members a complimentary live market update. These market updates will cover the current outlook and state of the industry.
Monday, June 28, 2010
Infineon intros 650V CoolMOS C6/E6 high-voltage power transistors
NEUBIBERG, GERMANY: Infineon Technologies has launched the new 650V CoolMOS C6/E6 series of high-performance power MOSFETs, combining the advantages of modern superjunction (SJ) devices such as low on-resistance and reduced capacitive switching losses with easy control of switching behaviour as well as high body diode ruggedness.
Based on the same technology platform, the C6 devices have been optimized for ease of use while the E6 devices have been designed to provide highest efficiency.
CoolMOS C6/E6 is the sixth generation of market leading high voltage SJ power MOSFETs from Infineon. The new 650V CoolMOS C6/E6 devices offer fast yet controlled switching performance and enable applications where efficiency and power density are key requirements.
The 650V CoolMOS C6/E6 products are easy to design-in and are the best choice for various energy efficient switching applications such as notebook adapters, solar, and other switched mode power supply (SMPS) designs where extra breakdown voltage headroom is required.
“With the new 650V C6/E6 product range Infineon complements its earlier released CoolMOS 600V C6/E6 product family, allowing us to offer the benefits of our sixth generation of CoolMOS™ technology in those applications where 650V blocking capability is desirable,” said Jan-Willem Reynaerts, Product Line Manager HVMOS Power Discretes at Infineon Technologies. “CoolMOS C6/E6 in that sense offers our customers an excellent migration path from our very successful 650V C3 series devices.”
Compared to the CoolMOS C3 650V family, the new 650V CoolMOS C6/E6 devices offer up to 20 percent lower energy storage in the output capacitance (E oss), and additionally the improved body diode of the C6/E6 devices shows higher ruggedness against hard commutation and reduces the reverse recovery charge by 25 percent. The switching behavior of the C6/E6 series is capable of avoiding excessive voltage and current slopes thanks to its balanced design with tuned gate resistors.
Samples of the IPA65R280C6/IPA65R280E6 (280mΩ in a TO220 FullPAK) and IPA65R380C6/IPA65R380E6 (380mΩ in a TO220 FullPAK) are available now. Volume production of these first parts of the new C6/E6 650V series will be started in July 2010. The product range will be steadily extended and is scheduled to be completed by the end of 2010.
Pricing for the IPA65R280C6/IPA65R280E6 is at $2.90 each for an order volume of 10,000 pieces.
Based on the same technology platform, the C6 devices have been optimized for ease of use while the E6 devices have been designed to provide highest efficiency.
CoolMOS C6/E6 is the sixth generation of market leading high voltage SJ power MOSFETs from Infineon. The new 650V CoolMOS C6/E6 devices offer fast yet controlled switching performance and enable applications where efficiency and power density are key requirements.
The 650V CoolMOS C6/E6 products are easy to design-in and are the best choice for various energy efficient switching applications such as notebook adapters, solar, and other switched mode power supply (SMPS) designs where extra breakdown voltage headroom is required.
“With the new 650V C6/E6 product range Infineon complements its earlier released CoolMOS 600V C6/E6 product family, allowing us to offer the benefits of our sixth generation of CoolMOS™ technology in those applications where 650V blocking capability is desirable,” said Jan-Willem Reynaerts, Product Line Manager HVMOS Power Discretes at Infineon Technologies. “CoolMOS C6/E6 in that sense offers our customers an excellent migration path from our very successful 650V C3 series devices.”
Compared to the CoolMOS C3 650V family, the new 650V CoolMOS C6/E6 devices offer up to 20 percent lower energy storage in the output capacitance (E oss), and additionally the improved body diode of the C6/E6 devices shows higher ruggedness against hard commutation and reduces the reverse recovery charge by 25 percent. The switching behavior of the C6/E6 series is capable of avoiding excessive voltage and current slopes thanks to its balanced design with tuned gate resistors.
Samples of the IPA65R280C6/IPA65R280E6 (280mΩ in a TO220 FullPAK) and IPA65R380C6/IPA65R380E6 (380mΩ in a TO220 FullPAK) are available now. Volume production of these first parts of the new C6/E6 650V series will be started in July 2010. The product range will be steadily extended and is scheduled to be completed by the end of 2010.
Pricing for the IPA65R280C6/IPA65R280E6 is at $2.90 each for an order volume of 10,000 pieces.
Lattice annouces v1.0 of its Lattice Diamond FPGA design software
HILLSBORO, USA: Lattice Semiconductor Ciorp. has announced Version 1.0 of its Lattice Diamond FPGA design software, the new flagship design environment for Lattice FPGA products. Lattice Diamond software provides a complete set of powerful tools, efficient design flows and modern user interface that enables designers to more quickly target low power, cost sensitive FPGA applications.
“We have used Lattice Diamond design software at Helion for the development of the Ionos line of video image processing pipeline IP, and were very impressed by the level of integration of so many different and powerful software tools into one GUI,” said Dr. Arndt Bussman, CTO of Helion GmbH. “This integration takes our FPGA code development process to unprecedented levels of design productivity and quality.”
“Diamond software gives our customers an easy to use, intuitive design environment that specifically addresses the critical design issues of cost sensitive, lower power applications. As designs become larger, and FPGAs are increasingly being used in more cost sensitive, high volume applications, designers need an easy to learn, flexible design environment for exploring different implementations to achieve their cost, power, and performance targets,” said Mike Kendrick, Lattice’s Manager of Software Product Planning.
“The Diamond software allows designers to efficiently manage these multiple implementations in one project. In addition, Diamond software continues to provide the industry-leading features previously released within our ispLEVER design environment that are specifically developed for low cost and low power applications. These include a very accurate power calculator, simultaneous switching output noise calculator, and the proven MAP and PAR FPGA implementation algorithms that take novel approaches to avoid congestion when targeting Lattice’s industry-leading FPGA product line.”
Intuitive modern user interface for a new generation of design tools
Diamond software enables designers to move quickly to the task at hand because navigation is direct and intuitive. Designers can manage their design view windows through the attach/detach feature.
This feature allows the activation of many alternate concurrent design views across the available screen space, yet avoids the clutter that could result without advanced window management. Combined with the extensive cross-probing between Diamond Views, designers can quickly investigate their design implementation’s utilization and critical timing.
Design exploration made easy
Diamond software supports multiple design Implementations. The design source can be shared among Implementations, or each Implementation can have its own unique design source. This allows design exploration from within the Diamond software: different approaches can be tried to evaluate their effect on design size, cost, performance and power.
Optimization options for logic synthesis and place and route are captured as a Strategy that can be applied easily to any of the Implementations. Diamond software comes with a library of pre-defined Strategies, and users can also create their own and add them to this library.
A single Strategy’s settings can be updated, for example to an alternate PAR algorithm tuned for highly connected designs, and run against several unique Implementations to determine if the results better meet the design goals for cost, power and performance. Finally, the Run Manager can launch a user-selected set of Implementations to be run through the flow, exploiting multi-core processors, if available, to improve the elapsed time to final results.
Improved designer productivity
The Diamond design environment includes many other design flow improvements that specifically improve designer productivity, particularly when targeting low power, cost sensitive applications. For example, built-in HDL visualization and code checking saves time by quickly catching coding errors and improving design documentation. As another example, designers can quickly find, investigate and address timing issues using the new Timing Analysis View.
The Timing Analysis View allows easy navigation of the static timing results. When timing constraints are revised, direct updates to timing analysis avoid the potentially significant time required to re-implement the design. Diamond software also includes extensive capabilities for scripting the design flow. Tcl command dictionaries specific to the Diamond design environment are available for projects, netlists, HDL code checking, power calculation and hardware debug insertion and analysis.
Expanded platform support
The Diamond design environment is supported on Windows and Linux. It includes support for Windows 7, and under Windows 7 64-bit, Diamond software has access to a full 4G memory space. This allows designers targeting even the largest LatticeECP3 devices unprecedented system performance and flexibility. The Diamond design environment includes support of Windows XP, Windows Vista (32 bit), and Windows 7 (32 bit and 64 bit), as well as Linux (Red Hat Enterprise Linux and Novell SUSE).
Other Lattice design software
Other Lattice design tools are available for download separately, including LatticeMico32 System and ispLEVER Classic, as well as the PAC‑Designer tools that target programmable mixed signal design. A Lattice Diamond license will also enable any of those tools that are under license control.
Third party tool support
Synopsys’ Synplify Pro advanced FPGA synthesis is included for all operating systems supported, and Aldec’s Active-HDL Lattice Edition II simulator is included for Windows.
In addition to the tool support for Lattice devices provided by the OEM versions of Synplify Pro and Active-HDL, Lattice devices are also supported by the full versions of Synopsys Synplify Pro and Aldec Active-HDL. Mentor Graphics ModelSim SE and Precision RTL synthesis also support the latest Lattice devices, such as the LatticeECP3 FPGA family.
Support for ispLEVER design software
Lattice will continue to support its ispLEVER tool suite for FPGA design over the next 18 months while transitioning its FPGA customer base to the Diamond design environment. There are no changes to the ispLEVER Classic product, which targets CPLD and legacy FPGA devices.
The Lattice Diamond software is available now for download from the Lattice website for both Windows and Linux. Once downloaded and installed, it can be used with either the Diamond free license or the Diamond subscription license.
The Diamond free license can be immediately generated upon request from the Lattice website and provides access to many popular Lattice devices such as the MachXO PLD family, the LatticeXP2 FPGA family and the LatticeECP2 FPGA family at no cost. The Diamond free license also enables Synopsys Synplify Pro for Lattice synthesis and Aldec Lattice Web Edition II simulation software.
The Diamond subscription license that can be purchased adds support for all Lattice FPGAs, including the latest LatticeECP3 devices. It enables Synopsys Synplify Pro for Lattice synthesis and the Aldec Lattice Edition II mixed language simulator for increased capacity and performance.
The Diamond subscription license enables both the new Diamond software and existing ispLEVER software from a single license. The Diamond subscription license price is $895 per year. All Lattice ispLEVER software users under active maintenance agreements will receive a Diamond subscription license for no charge that will expire one year from the Lattice Diamond 1.0 release date.
“We have used Lattice Diamond design software at Helion for the development of the Ionos line of video image processing pipeline IP, and were very impressed by the level of integration of so many different and powerful software tools into one GUI,” said Dr. Arndt Bussman, CTO of Helion GmbH. “This integration takes our FPGA code development process to unprecedented levels of design productivity and quality.”
“Diamond software gives our customers an easy to use, intuitive design environment that specifically addresses the critical design issues of cost sensitive, lower power applications. As designs become larger, and FPGAs are increasingly being used in more cost sensitive, high volume applications, designers need an easy to learn, flexible design environment for exploring different implementations to achieve their cost, power, and performance targets,” said Mike Kendrick, Lattice’s Manager of Software Product Planning.
“The Diamond software allows designers to efficiently manage these multiple implementations in one project. In addition, Diamond software continues to provide the industry-leading features previously released within our ispLEVER design environment that are specifically developed for low cost and low power applications. These include a very accurate power calculator, simultaneous switching output noise calculator, and the proven MAP and PAR FPGA implementation algorithms that take novel approaches to avoid congestion when targeting Lattice’s industry-leading FPGA product line.”
Intuitive modern user interface for a new generation of design tools
Diamond software enables designers to move quickly to the task at hand because navigation is direct and intuitive. Designers can manage their design view windows through the attach/detach feature.
This feature allows the activation of many alternate concurrent design views across the available screen space, yet avoids the clutter that could result without advanced window management. Combined with the extensive cross-probing between Diamond Views, designers can quickly investigate their design implementation’s utilization and critical timing.
Design exploration made easy
Diamond software supports multiple design Implementations. The design source can be shared among Implementations, or each Implementation can have its own unique design source. This allows design exploration from within the Diamond software: different approaches can be tried to evaluate their effect on design size, cost, performance and power.
Optimization options for logic synthesis and place and route are captured as a Strategy that can be applied easily to any of the Implementations. Diamond software comes with a library of pre-defined Strategies, and users can also create their own and add them to this library.
A single Strategy’s settings can be updated, for example to an alternate PAR algorithm tuned for highly connected designs, and run against several unique Implementations to determine if the results better meet the design goals for cost, power and performance. Finally, the Run Manager can launch a user-selected set of Implementations to be run through the flow, exploiting multi-core processors, if available, to improve the elapsed time to final results.
Improved designer productivity
The Diamond design environment includes many other design flow improvements that specifically improve designer productivity, particularly when targeting low power, cost sensitive applications. For example, built-in HDL visualization and code checking saves time by quickly catching coding errors and improving design documentation. As another example, designers can quickly find, investigate and address timing issues using the new Timing Analysis View.
The Timing Analysis View allows easy navigation of the static timing results. When timing constraints are revised, direct updates to timing analysis avoid the potentially significant time required to re-implement the design. Diamond software also includes extensive capabilities for scripting the design flow. Tcl command dictionaries specific to the Diamond design environment are available for projects, netlists, HDL code checking, power calculation and hardware debug insertion and analysis.
Expanded platform support
The Diamond design environment is supported on Windows and Linux. It includes support for Windows 7, and under Windows 7 64-bit, Diamond software has access to a full 4G memory space. This allows designers targeting even the largest LatticeECP3 devices unprecedented system performance and flexibility. The Diamond design environment includes support of Windows XP, Windows Vista (32 bit), and Windows 7 (32 bit and 64 bit), as well as Linux (Red Hat Enterprise Linux and Novell SUSE).
Other Lattice design software
Other Lattice design tools are available for download separately, including LatticeMico32 System and ispLEVER Classic, as well as the PAC‑Designer tools that target programmable mixed signal design. A Lattice Diamond license will also enable any of those tools that are under license control.
Third party tool support
Synopsys’ Synplify Pro advanced FPGA synthesis is included for all operating systems supported, and Aldec’s Active-HDL Lattice Edition II simulator is included for Windows.
In addition to the tool support for Lattice devices provided by the OEM versions of Synplify Pro and Active-HDL, Lattice devices are also supported by the full versions of Synopsys Synplify Pro and Aldec Active-HDL. Mentor Graphics ModelSim SE and Precision RTL synthesis also support the latest Lattice devices, such as the LatticeECP3 FPGA family.
Support for ispLEVER design software
Lattice will continue to support its ispLEVER tool suite for FPGA design over the next 18 months while transitioning its FPGA customer base to the Diamond design environment. There are no changes to the ispLEVER Classic product, which targets CPLD and legacy FPGA devices.
The Lattice Diamond software is available now for download from the Lattice website for both Windows and Linux. Once downloaded and installed, it can be used with either the Diamond free license or the Diamond subscription license.
The Diamond free license can be immediately generated upon request from the Lattice website and provides access to many popular Lattice devices such as the MachXO PLD family, the LatticeXP2 FPGA family and the LatticeECP2 FPGA family at no cost. The Diamond free license also enables Synopsys Synplify Pro for Lattice synthesis and Aldec Lattice Web Edition II simulation software.
The Diamond subscription license that can be purchased adds support for all Lattice FPGAs, including the latest LatticeECP3 devices. It enables Synopsys Synplify Pro for Lattice synthesis and the Aldec Lattice Edition II mixed language simulator for increased capacity and performance.
The Diamond subscription license enables both the new Diamond software and existing ispLEVER software from a single license. The Diamond subscription license price is $895 per year. All Lattice ispLEVER software users under active maintenance agreements will receive a Diamond subscription license for no charge that will expire one year from the Lattice Diamond 1.0 release date.
CamSemi C2163 enables low standby consumption for higher power apps
CAMBRIDGE, UK: CamSemi has announced a new addition to its existing C2160 family of Primary Side Sensing (PSS) controllers enabling manufacturers of higher power embedded and multiple output power supplies to fully exploit the cost benefits of bipolar transistors in developing lower cost and more energy-efficient solutions. The C2163 PSS controller is aimed at universal input adapters and chargers above 8 Watts.
C2163 delivers ultra-low standby power consumption and high efficiency power supplies for major applications such as networking products and set-top boxes, typically around 16 W but is also well suited for tablet computer and power tool chargers and other fast-growing, higher powered sectors.
The new controller uses low cost bipolar transistors to very significantly cut power supply system costs but without impacting performance. For example, a 12 W adapter based on C2163 delivers an average efficiency greater than 80% and a no-load power
consumption of less than 100 mW against the current Energy Star 2.0 requirement of 300 mW. But more importantly for manufacturers, the BOM cost is much lower compared with any of today’s more expensive MOSFET-based solutions.
“CamSemi’s new C2163 controller is the first of our products targeting higher power universal chargers and builds on the success we are achieving with our other PSS controllers in the mobile phone charger market. All the techniques we developed to cut no-load power consumption to less than 30 mW for 5 star-rated chargers have been utilised but at higher powers. C2163 is unique in combining low cost and energy efficiency with greater design and manufacturing flexibility where one controller can be utilised for multiple designs,” said David Baillie, CEO of CamSemi.
C2163 delivers the same key design benefits as the company’s existing PSS controller families including: ‘best in class’ voltage and current regulation without board level trimming; easily programmable cable compensation of up to 10 percent; switching frequency adjustment; and quasi-resonant switching to improve efficiency and reduce EMI. The C2163PX2 part is packaged in SOT23-6 and available in volume now.
An abbreviated C2163 datasheet is available from www.camsemi.com/support/datasheets with more detailed information, reference designs and other support from CamSemi or via one of the company’s distributors.
C2163 delivers ultra-low standby power consumption and high efficiency power supplies for major applications such as networking products and set-top boxes, typically around 16 W but is also well suited for tablet computer and power tool chargers and other fast-growing, higher powered sectors.
The new controller uses low cost bipolar transistors to very significantly cut power supply system costs but without impacting performance. For example, a 12 W adapter based on C2163 delivers an average efficiency greater than 80% and a no-load power
consumption of less than 100 mW against the current Energy Star 2.0 requirement of 300 mW. But more importantly for manufacturers, the BOM cost is much lower compared with any of today’s more expensive MOSFET-based solutions.
“CamSemi’s new C2163 controller is the first of our products targeting higher power universal chargers and builds on the success we are achieving with our other PSS controllers in the mobile phone charger market. All the techniques we developed to cut no-load power consumption to less than 30 mW for 5 star-rated chargers have been utilised but at higher powers. C2163 is unique in combining low cost and energy efficiency with greater design and manufacturing flexibility where one controller can be utilised for multiple designs,” said David Baillie, CEO of CamSemi.
C2163 delivers the same key design benefits as the company’s existing PSS controller families including: ‘best in class’ voltage and current regulation without board level trimming; easily programmable cable compensation of up to 10 percent; switching frequency adjustment; and quasi-resonant switching to improve efficiency and reduce EMI. The C2163PX2 part is packaged in SOT23-6 and available in volume now.
An abbreviated C2163 datasheet is available from www.camsemi.com/support/datasheets with more detailed information, reference designs and other support from CamSemi or via one of the company’s distributors.
Spreadtrum selects Teradyne UltraFLEX for testing 3G mobile baseband
NORTH READING, USA: Teradyne Inc. announced that Spreadtrum Communications Inc. has selected the UltraFLEX test system with the UltraPin800 digital channel card to test its dual mode HSDPA/TD-SCDMA and GSM/GPRS/EDGE mobile baseband devices. Spreadtrum’s integrated 3G mobile baseband SOCs are designed to support smart phones, feature phones and PC data card solutions.
“The mobile market in China demands highly integrated solutions that can be delivered quickly at low cost,” said Brian Chen, vice president of Operations of Spreadtrum. “The UltraFLEX platform multisite architecture provides cost effective test for our mobile baseband devices, and the IG-XL programming environment coupled with Teradyne’s applications support are critical for achieving our time-to-market goals.”
“The UltraFLEX platform with its SyncLink architecture, background DSP processing, and expansive portfolio of digital, mixed-signal and RF instrumentation enables us to provide highly cost effective multisite solutions for the next generation of mobile SOCs,” said Greg Smith, manager, Teradyne’s Broadband, Computing and Storage Business Unit.
“Spreadtrum is one of China’s leading TD-SCDMA baseband providers, and we are very pleased with its selection of the UltraFLEX. We look forward to working with Spreadtrum and its worldwide manufacturing partners as the mobile ecosystem continues to grow and evolve.”
"This design win reinforces Teradyne China’s ability to support local fabless companies who use the UltraFLEX platform for both engineering development and production," said SI Wei, vice president of Teradyne and Greater China Field Operations manager. "It proves again that Teradyne China’s local support infrastructure and technical skills provide a complete test solution from load board/probe card design, through program development to mass production for high-end SOC devices manufacturers in China."
“The mobile market in China demands highly integrated solutions that can be delivered quickly at low cost,” said Brian Chen, vice president of Operations of Spreadtrum. “The UltraFLEX platform multisite architecture provides cost effective test for our mobile baseband devices, and the IG-XL programming environment coupled with Teradyne’s applications support are critical for achieving our time-to-market goals.”
“The UltraFLEX platform with its SyncLink architecture, background DSP processing, and expansive portfolio of digital, mixed-signal and RF instrumentation enables us to provide highly cost effective multisite solutions for the next generation of mobile SOCs,” said Greg Smith, manager, Teradyne’s Broadband, Computing and Storage Business Unit.
“Spreadtrum is one of China’s leading TD-SCDMA baseband providers, and we are very pleased with its selection of the UltraFLEX. We look forward to working with Spreadtrum and its worldwide manufacturing partners as the mobile ecosystem continues to grow and evolve.”
"This design win reinforces Teradyne China’s ability to support local fabless companies who use the UltraFLEX platform for both engineering development and production," said SI Wei, vice president of Teradyne and Greater China Field Operations manager. "It proves again that Teradyne China’s local support infrastructure and technical skills provide a complete test solution from load board/probe card design, through program development to mass production for high-end SOC devices manufacturers in China."
SIA applauds release of IP Enforcement Joint Strategic Plan
SAN JOSE, USA: The Semiconductor Industry Association (SIA) has applauded the Administration’s release of the IP Enforcement Joint Strategic Plan as an important step to protect semiconductor intellectual property rights in the US and around the world.
“The national IP enforcement strategic plan will help protect the hard earned fruits of America’s substantial investment in research and development,” said SIA President George Scalise. “The semiconductor industry’s ability to continue to provide consumers with faster, smarter, and less expensive electronic devices depends on vigorous protection of intellectual property.”
The SIA submitted extensive comments in response to the White House’s request for recommendations. “We are particularly pleased that the plan calls for increased information sharing by Customs with IP rights holders so counterfeits can be quickly identified for seizure,” continued Scalise. “Semiconductors are widely used in a number of applications, including automotive controls, medical equipment, and critical infrastructure such as air traffic control, electric grid, and financial networks. It is very important that the industry and customs work closely to seize fake semiconductors at our nation’s borders.”
“The industry looks forward to working with the US Intellectual Property Enforcement Coordinator, Victoria Espinel, and her team on the implementation of the strategic plan.” concluded Scalise. In addition to the information sharing item, the enforcement action areas in which the industry expects to participate include encouraging the U.S. Government-Wide Working Group to Prevent US Government Purchase of Counterfeit Products to require government agencies to purchase directly from the manufacturer or authorized sources, to assist with international capacity building and training, and to support the coordination of law enforcement agencies targeted at semiconductor counterfeits.
Source: SIA, USA
“The national IP enforcement strategic plan will help protect the hard earned fruits of America’s substantial investment in research and development,” said SIA President George Scalise. “The semiconductor industry’s ability to continue to provide consumers with faster, smarter, and less expensive electronic devices depends on vigorous protection of intellectual property.”
The SIA submitted extensive comments in response to the White House’s request for recommendations. “We are particularly pleased that the plan calls for increased information sharing by Customs with IP rights holders so counterfeits can be quickly identified for seizure,” continued Scalise. “Semiconductors are widely used in a number of applications, including automotive controls, medical equipment, and critical infrastructure such as air traffic control, electric grid, and financial networks. It is very important that the industry and customs work closely to seize fake semiconductors at our nation’s borders.”
“The industry looks forward to working with the US Intellectual Property Enforcement Coordinator, Victoria Espinel, and her team on the implementation of the strategic plan.” concluded Scalise. In addition to the information sharing item, the enforcement action areas in which the industry expects to participate include encouraging the U.S. Government-Wide Working Group to Prevent US Government Purchase of Counterfeit Products to require government agencies to purchase directly from the manufacturer or authorized sources, to assist with international capacity building and training, and to support the coordination of law enforcement agencies targeted at semiconductor counterfeits.
Source: SIA, USA
Mentor Graphics adopts shareholder rights plan
WILSONVILLE, USA: Mentor Graphics Corp. announced that its Board of Directors has adopted a Shareholder Rights Plan in which one incentive stock purchase right will be distributed for each share of common stock held by shareholders of record as of the close of business on July 6, 2010.
The Rights are intended to enable the Board of Directors to protect the Company and to allow all of the Company’s shareholders to realize the long-term value of their investment in the Company. The issuance of the Rights is not intended to prevent a sale of control of the Company that is determined by the Board of Directors to be fair, advisable and in the best interests of all the Mentor Graphics shareholders. The Rights Plan provides that, unless redeemed earlier by the Company, the Rights will expire on December 31, 2011.
The Rights will be exercisable if a person or group, or any other person with whom they are acting in concert, without the approval of Mentor Graphics’ Board, acquires 15 percent or more of Mentor Graphics’ common stock or announces a tender offer for 15 percent or more of Mentor Graphics’ common stock. Under the Rights Plan, synthetic ownership of Mentor Graphics’ common stock in the form of derivative securities counts towards the 15 percent ownership threshold, if the investor or group physically owns 5 percent or more of the common stock.
The Rights also will be exercisable if a person or group that already owns 15 percent or more of Mentor Graphics’ common stock, without Board approval, acquires any additional shares (other than pursuant to a dividend or distribution paid or made by the Company or pursuant to a stock split or subdivision). The Company’s existing stockholders, if any, that beneficially own in excess of 15 percent of the common stock will be “grandfathered in.”
If the Rights become exercisable, all Rights holders (other than the person or group triggering the Rights) will be entitled to purchase Mentor Graphics’ common stock at a 50 percent discount. Rights held by the person or group triggering the Rights will become void and will not be exercisable.
The distribution of the Rights is not taxable to shareholders. The Rights will trade with Mentor Graphics’ common stock and Mentor Graphics’ Board may terminate the Rights Plan or redeem the Rights prior to the time the Rights are triggered. Further details about the Rights Plan will be contained in a Form 8-K to be filed with the Securities and Exchange Commission by the Company.
The Rights are intended to enable the Board of Directors to protect the Company and to allow all of the Company’s shareholders to realize the long-term value of their investment in the Company. The issuance of the Rights is not intended to prevent a sale of control of the Company that is determined by the Board of Directors to be fair, advisable and in the best interests of all the Mentor Graphics shareholders. The Rights Plan provides that, unless redeemed earlier by the Company, the Rights will expire on December 31, 2011.
The Rights will be exercisable if a person or group, or any other person with whom they are acting in concert, without the approval of Mentor Graphics’ Board, acquires 15 percent or more of Mentor Graphics’ common stock or announces a tender offer for 15 percent or more of Mentor Graphics’ common stock. Under the Rights Plan, synthetic ownership of Mentor Graphics’ common stock in the form of derivative securities counts towards the 15 percent ownership threshold, if the investor or group physically owns 5 percent or more of the common stock.
The Rights also will be exercisable if a person or group that already owns 15 percent or more of Mentor Graphics’ common stock, without Board approval, acquires any additional shares (other than pursuant to a dividend or distribution paid or made by the Company or pursuant to a stock split or subdivision). The Company’s existing stockholders, if any, that beneficially own in excess of 15 percent of the common stock will be “grandfathered in.”
If the Rights become exercisable, all Rights holders (other than the person or group triggering the Rights) will be entitled to purchase Mentor Graphics’ common stock at a 50 percent discount. Rights held by the person or group triggering the Rights will become void and will not be exercisable.
The distribution of the Rights is not taxable to shareholders. The Rights will trade with Mentor Graphics’ common stock and Mentor Graphics’ Board may terminate the Rights Plan or redeem the Rights prior to the time the Rights are triggered. Further details about the Rights Plan will be contained in a Form 8-K to be filed with the Securities and Exchange Commission by the Company.
Saturday, June 26, 2010
Silvaco announces UMC-qualified PDK for 0.18um CMOS process
SANTA CLARA, USA: Silvaco Inc., a leading provider of TCAD and EDA software, announced that United Microelectronics Corp. (UMC), a leading global semiconductor foundry, has completed qualifying Silvaco’s Process Design Kit for UMC’s 0.18um CMOS process.
UMC now officially supports Silvaco's analog/mixed-Signal IC design flow. This design kit includes a symbol library for the Gateway schematic capture software and parameterized layout generators for the Expert layout editor.
“We are glad to partner with Silvaco in the development and validation of the Silvaco process design kit,” said Stephen Fu, division director of IP development and design support at UMC. “With the release of qualified Process Design Kits, integrated circuit designers can easily and effectively leverage the readiness of our analog and mixed signal technologies to jump-start customers' design activities.”
“The partnership between UMC and Silvaco has supported IC designers in their requirements to complete designs efficiently,” said Daniel Chang, director of applications engineering and foundry support division at Silvaco. “I'm very pleased to see this collaboration elevated to the next level. With the support of UMC-PDKs, we are enabling our mutual customers to design in UMC's leading technologies.”
UMC now officially supports Silvaco's analog/mixed-Signal IC design flow. This design kit includes a symbol library for the Gateway schematic capture software and parameterized layout generators for the Expert layout editor.
“We are glad to partner with Silvaco in the development and validation of the Silvaco process design kit,” said Stephen Fu, division director of IP development and design support at UMC. “With the release of qualified Process Design Kits, integrated circuit designers can easily and effectively leverage the readiness of our analog and mixed signal technologies to jump-start customers' design activities.”
“The partnership between UMC and Silvaco has supported IC designers in their requirements to complete designs efficiently,” said Daniel Chang, director of applications engineering and foundry support division at Silvaco. “I'm very pleased to see this collaboration elevated to the next level. With the support of UMC-PDKs, we are enabling our mutual customers to design in UMC's leading technologies.”
IntelliSense and ClassOne Equipment form strategic partnership in China fab
NANJING, CHINA: MEMS design and development company IntelliSense today announced that it has purchased the bulk of its semiconductor process equipment for it’s new fab in Nanjing, China, from refurbished equipment supplier ClassOne Equipment. The alliance went so well that the two companies have formed a strategic partnership to continue the relationship.
For almost 20 years IntelliSense has provided MEMS design software, IP and consulting services. Earlier this year, IntelliSense entered into an agreement to purchase late vintage MEMS fab equipment from ClassOne to equip a new facility just completed in Nanjing, China.
The equipment purchased included tools such as EVG mask aligners, EVG wafer bonders, EVG Coat Tracks, Wet Benches, KLA-Tencor wafer inspection systems, and other standard wafer fabrication and metrology equipment. The fabrication line will enable IntelliSense to manufacture in demand MEMS products to meet client requirements.
The IntelliSense facility will offer the China market a total MEMS solution business model, providing its customers with the ability to take a MEMS product from design to prototype production.
Strategic partnership details
ClassOne Equipment is announcing today that it has appointed IntelliSense as its official representative in China. To strengthen the relationship, ClassOne will open an office inside the IntelliSense facility and feature the IntelliSense fab as a showroom and demonstration lab of its equipment offerings and refurbishment capabilities to prospective mainland China clients.
“This partnership will allow us to expand our existing China business,” commented Xiaoduo Zhang, China market manager for IntelliSense. “With an established process cleanroom and equipment demo lab, which ClassOne Equipment helped us build, we can demonstrate our ‘total MEMS solution’ to existing and new clients. This will be a valuable resource to show our rapid response and best-in-class service to clients in China and Southeast Asia.”
“This strategic partnership with IntelliSense strengthens our foothold in China,” commented Byron Exarcos, president of ClassOne Equipment. “Not only does it demonstrate that we can single-handedly equip an entire fab, but now we’ll be able to reference the IntelliSense facility to illustrate the benefits of refurbished equipment. China has been major consumer of refurbishment equipment over the past several years. The IntelliSense Nanjing fab will only increase that trend.”
For almost 20 years IntelliSense has provided MEMS design software, IP and consulting services. Earlier this year, IntelliSense entered into an agreement to purchase late vintage MEMS fab equipment from ClassOne to equip a new facility just completed in Nanjing, China.
The equipment purchased included tools such as EVG mask aligners, EVG wafer bonders, EVG Coat Tracks, Wet Benches, KLA-Tencor wafer inspection systems, and other standard wafer fabrication and metrology equipment. The fabrication line will enable IntelliSense to manufacture in demand MEMS products to meet client requirements.
The IntelliSense facility will offer the China market a total MEMS solution business model, providing its customers with the ability to take a MEMS product from design to prototype production.
Strategic partnership details
ClassOne Equipment is announcing today that it has appointed IntelliSense as its official representative in China. To strengthen the relationship, ClassOne will open an office inside the IntelliSense facility and feature the IntelliSense fab as a showroom and demonstration lab of its equipment offerings and refurbishment capabilities to prospective mainland China clients.
“This partnership will allow us to expand our existing China business,” commented Xiaoduo Zhang, China market manager for IntelliSense. “With an established process cleanroom and equipment demo lab, which ClassOne Equipment helped us build, we can demonstrate our ‘total MEMS solution’ to existing and new clients. This will be a valuable resource to show our rapid response and best-in-class service to clients in China and Southeast Asia.”
“This strategic partnership with IntelliSense strengthens our foothold in China,” commented Byron Exarcos, president of ClassOne Equipment. “Not only does it demonstrate that we can single-handedly equip an entire fab, but now we’ll be able to reference the IntelliSense facility to illustrate the benefits of refurbished equipment. China has been major consumer of refurbishment equipment over the past several years. The IntelliSense Nanjing fab will only increase that trend.”
Actel announces power management solution for SmartFusion intelligent mixed signal FPGAs
MOUNTAIN VIEW, USA: Actel Corp. has announced a power management solution for its newly introduced SmartFusion intelligent mixed signal FPGAs.
Actel's Mixed Signal Power Manager (MPM) Solution includes a complete reference design with graphical configurator to enter power sequencing and trimming requirements. The design takes full advantage of the capabilities of SmartFusion devices and is targeted to the MPM Daughter Card which can be used with either the SmartFusion Evaluation Kit or SmartFusion Development Kit. This complete power management solution enables the integration of power rail management into embedded designs.
The SmartFusion MPM solution delivers advanced power management that is easily configured via a configuration GUI, enabling system designers to effortlessly integrate and configure intelligent power management with their ARM Cortex-M3 based embedded designs. Actel's graphical design configuration approach enables power management thresholds to be set, voltage trimming to be configured and sequencing functionality to be updated without changing the circuitry programmed into the FPGA fabric.
SmartFusion MPM demonstrates power-up sequencing, management and power down sequencing of up to 32 independent power regulators (rails) with 8 rails supporting closed loop voltage trimming using PWM. Also demonstrated are five user configurable flags per regulator channel, exponential decay filtering, and up to 32 digital 'trigger' outputs using single level combinatorial logic, enabling the combination of internal states with 32 corresponding off-chip digital inputs to build complex system-level state signaling.
Available for purchase now are the SmartFusion Evaluation Kit (A2F-EVAL-KIT, list price $99), SmartFusion Development Kit (A2F-DEV-KIT, list price $999) and MPM Daughter Card Kit (MPM-DC-KIT, list price $299).
Actel's Mixed Signal Power Manager (MPM) Solution includes a complete reference design with graphical configurator to enter power sequencing and trimming requirements. The design takes full advantage of the capabilities of SmartFusion devices and is targeted to the MPM Daughter Card which can be used with either the SmartFusion Evaluation Kit or SmartFusion Development Kit. This complete power management solution enables the integration of power rail management into embedded designs.
The SmartFusion MPM solution delivers advanced power management that is easily configured via a configuration GUI, enabling system designers to effortlessly integrate and configure intelligent power management with their ARM Cortex-M3 based embedded designs. Actel's graphical design configuration approach enables power management thresholds to be set, voltage trimming to be configured and sequencing functionality to be updated without changing the circuitry programmed into the FPGA fabric.
SmartFusion MPM demonstrates power-up sequencing, management and power down sequencing of up to 32 independent power regulators (rails) with 8 rails supporting closed loop voltage trimming using PWM. Also demonstrated are five user configurable flags per regulator channel, exponential decay filtering, and up to 32 digital 'trigger' outputs using single level combinatorial logic, enabling the combination of internal states with 32 corresponding off-chip digital inputs to build complex system-level state signaling.
Available for purchase now are the SmartFusion Evaluation Kit (A2F-EVAL-KIT, list price $99), SmartFusion Development Kit (A2F-DEV-KIT, list price $999) and MPM Daughter Card Kit (MPM-DC-KIT, list price $299).
ITC confirms MPS patent victory against O2 Micro
SAN JOSE, USA: Monolithic Power Systems (MPS) (Nasdaq: MPWR), a leading fabless manufacturer of high-performance analog and mixed-signal semiconductors, announced the US International Trade Commission issued a final determination finding no violation of Section 337 by MPS or its customers in an action brought by O2 Micro International Ltd. in 2008.
An ITC administrative law judge had previously issued an initial determination in April that also found no violation. The ITC's final determination concludes that none of MPS' accused products infringe O2 Micro's US Patent No. 7,417,382 (the '382 patent).
In a related district court action, which is pending in the United States District Court for the Northern District of California, O2 Micro has filed a motion to dismiss its claims for infringement of the '382 patent, with prejudice, and has covenanted not to sue MPS or any MPS distributors or customers for infringement of the '382 patent based on any past and current MPS products. MPS expects to seek attorney fees against O2 Micro once the judgment is entered dismissing the action.
MPS is represented in this case by Finnegan, Henderson, Farabow, Garrett & Dunner LLP and Latham & Watkins LLP. MPS trial counsel includes Smith Brittingham, Dean Dunlavey, Lionel Lavenue, Mark Flagel, Darren Jirron, Scott Mosko and Franklin Kang.
An ITC administrative law judge had previously issued an initial determination in April that also found no violation. The ITC's final determination concludes that none of MPS' accused products infringe O2 Micro's US Patent No. 7,417,382 (the '382 patent).
In a related district court action, which is pending in the United States District Court for the Northern District of California, O2 Micro has filed a motion to dismiss its claims for infringement of the '382 patent, with prejudice, and has covenanted not to sue MPS or any MPS distributors or customers for infringement of the '382 patent based on any past and current MPS products. MPS expects to seek attorney fees against O2 Micro once the judgment is entered dismissing the action.
MPS is represented in this case by Finnegan, Henderson, Farabow, Garrett & Dunner LLP and Latham & Watkins LLP. MPS trial counsel includes Smith Brittingham, Dean Dunlavey, Lionel Lavenue, Mark Flagel, Darren Jirron, Scott Mosko and Franklin Kang.
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