CANADA, KOREA & USA: MagnaChip Semiconductor Corp., a Korea-based designer and manufacturer of analog and mixed-signal semiconductor products, and Sidense Corp., a leading developer of Logic Non-Volatile Memory (LNVM) one-time programmable (OTP) memory IP cores announced that Sidense's SLP 1T-OTP macros have been fully qualified for MagnaChip's 180nm 1.8/3.3/18V high voltage CMOS and mixed-signal process.
Semiconductor devices fabricated in these processes are used in applications such as LED lighting controllers, display controllers and power-management ICs (PMICs) for mobile and other high-volume applications.
"Leading semiconductor device manufacturers are already using Sidense 1T-OTP macros for LED energy management solutions fabricated using MagnaChip's leading process technology," stated Tom Schild, Sidense's VP of Worldwide Sales and Marketing. "By offering our very dense and low-power SLP memory macros in MagnaChip's HV process, customers have a proven platform in which they can take full advantage of the benefits of 1T-OTP memory and its cost-effectiveness, reliability and security advantages over eFuse, mask ROM and other NVM technologies."
"Qualifying Sidense's SLP 1T-OTP memory macros in our high-voltage and mixed-signal processes with high performance analog devices such as low noise and multi Vt transistors allows us to provide our key customers with significant benefits in performance and die area savings as well as long term reliability at high temperatures," said Namkyu Park, senior VP of Marketing for MagnaChip's Semiconductor Manufacturing Services Division.
"By using MagnaChip's specialized process technology with Sidense's reliable and cost-effective non-volatile memory macros, customers can bring to market products that offer distinct advantages over those of their competitors having flexible analog trimming and/or control program storage."
Monday, March 25, 2013
Imagination and TSMC strengthen technology collaboration
ENGLAND & TAIWAN: TSMC and Imagination Technologies have announced the next phase of their technology collaboration.
As part of this new phase of their relationship, Imagination will work closely with TSMC to develop highly optimised reference design flows and silicon implementations using Imagination's industry-leading PowerVR Series6 GPUs combined with TSMC's advanced process technologies, including 16-nanometer (nm) FinFET process technology.
Imagination and TSMC R&D teams will also work together to create fully characterised reference system designs, utilizing high bandwidth memory standards and TSMC's 3D IC technology capability to demonstrate new levels of system performance and capabilities while retaining all the essential characteristics of power, silicon area and small package footprint demanded by high volume mobile SoCs.
As GPUs increasingly dominate the area, power and performance of next generation SoCs and the options available to designers using advanced silicon processes become more complex, design flows and libraries need to be optimally tuned to enable design teams to achieve the best possible performance, power consumption and silicon area in ever more demanding timescales.
To address these challenges, Imagination and TSMC are investigating how the characteristics of the latest processes, such as 16FinFET, influence the design of high performance IP-based SoCs.
As part of this new phase of their relationship, Imagination will work closely with TSMC to develop highly optimised reference design flows and silicon implementations using Imagination's industry-leading PowerVR Series6 GPUs combined with TSMC's advanced process technologies, including 16-nanometer (nm) FinFET process technology.
Imagination and TSMC R&D teams will also work together to create fully characterised reference system designs, utilizing high bandwidth memory standards and TSMC's 3D IC technology capability to demonstrate new levels of system performance and capabilities while retaining all the essential characteristics of power, silicon area and small package footprint demanded by high volume mobile SoCs.
As GPUs increasingly dominate the area, power and performance of next generation SoCs and the options available to designers using advanced silicon processes become more complex, design flows and libraries need to be optimally tuned to enable design teams to achieve the best possible performance, power consumption and silicon area in ever more demanding timescales.
To address these challenges, Imagination and TSMC are investigating how the characteristics of the latest processes, such as 16FinFET, influence the design of high performance IP-based SoCs.
Fujitsu Semiconductor releases 1 Mbit and 2 Mbit FRAM products
SINGAPORE: Fujitsu Semiconductor Asia Pte Ltd (FSAL) announced the development of two new FRAM products, MB85RS1MT and MB85RS2MT, which feature 1 Mbit and 2 Mbit of memory,
respectively, making them the largest density serial-interface FRAM products offered by Fujitsu Semiconductor.
The two new FRAM products guarantee 10 trillion read/write cycles, roughly ten times more than existing chips, making them optimal for use in applications such as smart meters, industrial machinery and medical devices. Compared to identical density EEPROM, MB85RS1MT and MB85RS2MT consume 92 percent less power during writing.
In addition, because the new FRAM products can incorporate all the technology required for system memory components—which have typically consisted of EEPROM, SRAM and a battery for data retention—into a single chip, it is possible to substantially reduce component costs, mounted area, and power consumption.
This, in turn, will also greatly contribute to the development of smaller, power-efficient equipment for which maintenance can be easily performed, since backup battery is not necessary.
The new products will be made available in sample quantities starting end of March 2013.
FRAM is a type of memory that features both non-volatility, which allows data to be retained even when the power is switched off, and random access, which enables fast data writing. Because FRAM can safely store data that is being written even during sudden power source failures and power outages, it is possible to ensure the protection of equipment information and data recorded immediately preceding a power source outage.
Based on this capability, since launching volume production in 1999 FRAM products from Fujitsu Semiconductor have been widely employed for use primarily in factory automation equipment, measurement devices, banking terminals, and medical devices.
As an update to its lineup of FRAM products, Fujitsu Semiconductor has recently developed MB85RS1MT (1 Mbit) and MB85RS2MT (2 Mbit), which represent the company’s largest density FRAM products to date to feature an SPI serial interface. Both products feature an improved guaranteed read/write cycle count of 10 trillion cycles, which is ten times more than Fujitsu’s existing FRAM products, providing even better support for real-time, continuous data recording.
For applications including smart meters and other measurement devices, as well as industrial machinery and medical devices such as hearing aids—all of which to date have required 1-2 Mbit non-volatile memory with a serial interface—it is now possible to replace conventional EEPROM with Fujitsu Semiconductor’s new FRAM products.
The resulting improvements in fast writing can lead to greater performance, while also minimizing the risk of data loss from sudden voltage drops or power outages. In terms of power consumed during writing, as well, the new products consume 92 percent less power than EEPROM, thereby helping to extend battery life.
Moreover, for industrial machinery that employs SRAM for data recording and EEPROM for storing parameters and programs, the new FRAM products can incorporate these capabilities into a single chip, allowing for a reduction in the number of memory components required and obviating the need for batteries for data retention.
The memory itself can also be shrunk into a smaller package size, making it possible to reduce the mounted area required for memory components by over 90%. As a result, the new FRAM products help to reduce the size of end products, eliminate the need for battery replacement maintenance, and cut power consumption, in addition to contributing to lower component costs.
Going forward, Fujitsu Semiconductor will continue to deliver solutions that assist customers in improving the performance of end products, in facilitating maintenance on live equipment, and in minimizing risk.
respectively, making them the largest density serial-interface FRAM products offered by Fujitsu Semiconductor.
The two new FRAM products guarantee 10 trillion read/write cycles, roughly ten times more than existing chips, making them optimal for use in applications such as smart meters, industrial machinery and medical devices. Compared to identical density EEPROM, MB85RS1MT and MB85RS2MT consume 92 percent less power during writing.
In addition, because the new FRAM products can incorporate all the technology required for system memory components—which have typically consisted of EEPROM, SRAM and a battery for data retention—into a single chip, it is possible to substantially reduce component costs, mounted area, and power consumption.
This, in turn, will also greatly contribute to the development of smaller, power-efficient equipment for which maintenance can be easily performed, since backup battery is not necessary.
The new products will be made available in sample quantities starting end of March 2013.
Based on this capability, since launching volume production in 1999 FRAM products from Fujitsu Semiconductor have been widely employed for use primarily in factory automation equipment, measurement devices, banking terminals, and medical devices.
As an update to its lineup of FRAM products, Fujitsu Semiconductor has recently developed MB85RS1MT (1 Mbit) and MB85RS2MT (2 Mbit), which represent the company’s largest density FRAM products to date to feature an SPI serial interface. Both products feature an improved guaranteed read/write cycle count of 10 trillion cycles, which is ten times more than Fujitsu’s existing FRAM products, providing even better support for real-time, continuous data recording.
For applications including smart meters and other measurement devices, as well as industrial machinery and medical devices such as hearing aids—all of which to date have required 1-2 Mbit non-volatile memory with a serial interface—it is now possible to replace conventional EEPROM with Fujitsu Semiconductor’s new FRAM products.
The resulting improvements in fast writing can lead to greater performance, while also minimizing the risk of data loss from sudden voltage drops or power outages. In terms of power consumed during writing, as well, the new products consume 92 percent less power than EEPROM, thereby helping to extend battery life.
Moreover, for industrial machinery that employs SRAM for data recording and EEPROM for storing parameters and programs, the new FRAM products can incorporate these capabilities into a single chip, allowing for a reduction in the number of memory components required and obviating the need for batteries for data retention.
The memory itself can also be shrunk into a smaller package size, making it possible to reduce the mounted area required for memory components by over 90%. As a result, the new FRAM products help to reduce the size of end products, eliminate the need for battery replacement maintenance, and cut power consumption, in addition to contributing to lower component costs.
Going forward, Fujitsu Semiconductor will continue to deliver solutions that assist customers in improving the performance of end products, in facilitating maintenance on live equipment, and in minimizing risk.
Friday, March 22, 2013
North American semiconductor equipment industry posts February 2013 book-to-bill ratio of 1.10
USA: North America-based manufacturers of semiconductor equipment posted $1.07 billion in orders worldwide in February 2013 (three-month average basis) and a book-to-bill ratio of 1.10, according to the February Book-to-Bill Report published by SEMI. A book-to-bill of 1.10 means that $110 worth of orders were received for every $100 of product billed for the month.
The three-month average of worldwide bookings in February 2013 was $1.07 billion. The bookings figure is 0.2 percent lower than the final January 2013 level of $1.08 billion, and is 19.7 percent lower than the February 2012 order level of $1.34 billion.
The three-month average of worldwide billings in February 2013 was $975.3 million. The billings figure is 0.8 percent higher than the final January 2013 level of $968.0 million, and is 26.3 percent lower than the February 2012 billings level of $1.32 billion.
“Three-month average bookings and billings posted by North American semiconductor equipment providers remain above parity and consistent with prior month levels," said Denny McGuirk, president and CEO of SEMI. "We expect modest investment by semiconductor makers in the first half of the year with foundry and advanced packaging technology among the near-term spending drivers.”
The three-month average of worldwide bookings in February 2013 was $1.07 billion. The bookings figure is 0.2 percent lower than the final January 2013 level of $1.08 billion, and is 19.7 percent lower than the February 2012 order level of $1.34 billion.
The three-month average of worldwide billings in February 2013 was $975.3 million. The billings figure is 0.8 percent higher than the final January 2013 level of $968.0 million, and is 26.3 percent lower than the February 2012 billings level of $1.32 billion.
“Three-month average bookings and billings posted by North American semiconductor equipment providers remain above parity and consistent with prior month levels," said Denny McGuirk, president and CEO of SEMI. "We expect modest investment by semiconductor makers in the first half of the year with foundry and advanced packaging technology among the near-term spending drivers.”
Toshiba develops low power OS for many-core LSI for embedded apps
Design Automation & Test in Europe 2013, JAPAN: Toshiba Corp. has developed an innovative, low power operating system (OS) for many-core processors, targeting application in embedded systems, including automotive products and digital consumer products.
An evaluation of the OS on the company's own many-core processor recorded a 24.6 percent power reduction against the standard OS when running a super resolution program that scaled 1920x1080 pixel images to 3840x2160 resolutions. Details of the new OS were presented at "Design, Automation & Test in Europe (DATE 2013)" in Grenoble, France on March 20.
Recent multimedia processing, including video encoding and decoding and image recognition, requires high performance processors. Many-core processors, with up to dozens of cores, are finding an important role in running these applications. However, there is a problem: the higher the number of cores, the higher total power consumption. Manufactures want low power systems in order to maximize the battery life of mobile devices, and in consideration of the environment.
In current methodology, the OS controls power to the processor based on computation load history. However, this approach is not accurate enough to reduce power consumption and fails to manage abrupt fluctuations in computation load, and so more power than necessary is consumed.
Toshiba's many-core processor OS achieves low power consumption by using information inherent to parallel programs to control power supply. Parallel programs are run by a thread unit, and to run correctly the order for executing the threads must be specified.
Toshiba has developed and employed a technique for specifying the "number of dependence" among threads and controlling the execution order. This approach recognizes that the dependency number at any given time closely foreshadows the computation load in the near future, securing a more accurate prediction of power requirements. The new OS controls power supply and achieves a low power system without degradation in performance.
Toshiba plans to apply the low power OS to embedded systems for such applications as high resolution image processing and image recognition.
An evaluation of the OS on the company's own many-core processor recorded a 24.6 percent power reduction against the standard OS when running a super resolution program that scaled 1920x1080 pixel images to 3840x2160 resolutions. Details of the new OS were presented at "Design, Automation & Test in Europe (DATE 2013)" in Grenoble, France on March 20.
Recent multimedia processing, including video encoding and decoding and image recognition, requires high performance processors. Many-core processors, with up to dozens of cores, are finding an important role in running these applications. However, there is a problem: the higher the number of cores, the higher total power consumption. Manufactures want low power systems in order to maximize the battery life of mobile devices, and in consideration of the environment.
In current methodology, the OS controls power to the processor based on computation load history. However, this approach is not accurate enough to reduce power consumption and fails to manage abrupt fluctuations in computation load, and so more power than necessary is consumed.
Toshiba's many-core processor OS achieves low power consumption by using information inherent to parallel programs to control power supply. Parallel programs are run by a thread unit, and to run correctly the order for executing the threads must be specified.
Toshiba has developed and employed a technique for specifying the "number of dependence" among threads and controlling the execution order. This approach recognizes that the dependency number at any given time closely foreshadows the computation load in the near future, securing a more accurate prediction of power requirements. The new OS controls power supply and achieves a low power system without degradation in performance.
Toshiba plans to apply the low power OS to embedded systems for such applications as high resolution image processing and image recognition.
Lattice announces world's smallest FPGA for miniature systems
USA: Lattice Semiconductor Corp. announced the iCE40 LP384 FPGA, the smallest member of its expanding iCE40 family of ultra-low density FPGAs.
Enabling designers to rapidly add new features and differentiate cost-sensitive, space-constrained, low-power products, the new small footprint FPGA is ideal for applications such as portable medical monitors, smartphones, digital cameras, eReaders, and compact embedded systems.
The tiny, low power, low cost iCE40 LP384 FPGA has a capacity of 384 LUTs; consumes 25-Microwatts static core power; comes in packages as small as 2.5 mm x 2.5 mm with a migration path to 2.0 mm x 2.0 mm and costs less than 50 cents per unit in multi-million unit quantities.
"While system footprints continue to shrink, designers must constantly search for new ways to add more functionality so they can process more information," said Brent Przybus, senior director of corporate and product marketing at Lattice Semiconductor.
"The iCE40 LP384 FPGA offers the perfect architecture for capturing and processing large amounts of data at hardware speeds while using very little power and board space. It deftly handles system tasks such as managing sensor interfaces, adapting to new interface standards, and offloading the CPU without requiring fully custom-designed chips."
The exponential growth of handheld applications is creating new challenges for hardware designers. Many new applications today connect end users with data collected from a growing number of sensors that measure natural phenomena such as temperature, moisture, light, and positioning. At the same time, the growing use of video is driving the deployment of new low power, display technology that not only enhances the visual experience, but does so without breaking stringent power budgets.
Moreover, small automated control units are now being used to maximize energy efficiency and security in buildings and homes by responding to light, infrared, noise, and by adjusting fans, blinds, and temperature controls. Designers of these types of equipment must find ways to shrink the size of their systems while differentiating their products from competitive market offerings.
Enabling designers to rapidly add new features and differentiate cost-sensitive, space-constrained, low-power products, the new small footprint FPGA is ideal for applications such as portable medical monitors, smartphones, digital cameras, eReaders, and compact embedded systems.
The tiny, low power, low cost iCE40 LP384 FPGA has a capacity of 384 LUTs; consumes 25-Microwatts static core power; comes in packages as small as 2.5 mm x 2.5 mm with a migration path to 2.0 mm x 2.0 mm and costs less than 50 cents per unit in multi-million unit quantities.
"While system footprints continue to shrink, designers must constantly search for new ways to add more functionality so they can process more information," said Brent Przybus, senior director of corporate and product marketing at Lattice Semiconductor.
"The iCE40 LP384 FPGA offers the perfect architecture for capturing and processing large amounts of data at hardware speeds while using very little power and board space. It deftly handles system tasks such as managing sensor interfaces, adapting to new interface standards, and offloading the CPU without requiring fully custom-designed chips."
The exponential growth of handheld applications is creating new challenges for hardware designers. Many new applications today connect end users with data collected from a growing number of sensors that measure natural phenomena such as temperature, moisture, light, and positioning. At the same time, the growing use of video is driving the deployment of new low power, display technology that not only enhances the visual experience, but does so without breaking stringent power budgets.
Moreover, small automated control units are now being used to maximize energy efficiency and security in buildings and homes by responding to light, infrared, noise, and by adjusting fans, blinds, and temperature controls. Designers of these types of equipment must find ways to shrink the size of their systems while differentiating their products from competitive market offerings.
NXP launches industry’s first automotive-grade isolated CAN transceiver
SINGAPORE: Building on its industry-leading position in In-Vehicle Networking, NXP Semiconductors N.V. introduced the TJA1052i, a high-speed Controller Area Network (CAN) transceiver with integrated galvanic isolation technology.
The TJA1052i is the first ISO11898-2 compliant product of its kind to offer this level of integration at AEC-Q100 automotive grade quality.
The TJA1052i is an excellent choice for all types of CAN networks where high- and low-voltage networks co-exist – such as in electric and hybrid vehicles – and require galvanic isolation for safety reasons.
Adding isolation to the CAN transceiver significantly simplifies the design effort to safely bridge between high and low voltage levels. The TJA1052i provides protection against electric shocks, overvoltage, ground offset and reverse current, while significantly improving signal integrity in noisy electromagnetic environments.
By integrating an existing market accepted CAN transceiver with a Galvanic Isolator in one package, this new solution ensures matching dynamic parameters, reduces board space, improves signal performance, and increases overall reliability and cost-effectiveness.
Historically, automotive OEMs and Tier 1 suppliers have used expensive Opto Couplers to isolate the CAN transceiver, with performance in such a standalone solution tending to degrade over time.
The TJA1052i is well-suited for the growing market of hybrid and full electric vehicles (H/EVs), where high and low voltage levels co-exist. H/EVs are equipped with multiple battery modules – typically controlled via CAN by the Battery Management System – which together can supply up to 500 Volts and also power other high-voltage applications such as inverter, start/stop, DC/DC converter, charger and air conditioning systems.
These systems need to communicate with other electronic control units (ECUs) via the CAN Bus, and are typically operated from the 12V board net.
Isolated CAN products are also needed in industrial applications where ECUs controlling high voltage applications and other ECUs need to be connected to each other via the CAN bus. Application examples for the TJA1052i in non-automotive areas are industrial equipment, energy storage systems, building automation and H/EV charging stations.
“The TJA1052i is another great example of NXP’s strategy to both connect the car and improve energy efficiency – even under challenging conditions,” said Toni Versluijs, VP and GM, in-vehicle networking business, NXP Semiconductors.
“Our third-generation automotive CAN transceivers are already approved and used by multiple OEMs. By integrating galvanic isolation into the TJA1052i, we are first in the industry to deliver an automotive-grade solution that saves both space and money, while making it easier for our customers to build and connect their ECUs.”
The TJA1052i is ramping up in production with immediate effect.
The TJA1052i is the first ISO11898-2 compliant product of its kind to offer this level of integration at AEC-Q100 automotive grade quality.
The TJA1052i is an excellent choice for all types of CAN networks where high- and low-voltage networks co-exist – such as in electric and hybrid vehicles – and require galvanic isolation for safety reasons.
Adding isolation to the CAN transceiver significantly simplifies the design effort to safely bridge between high and low voltage levels. The TJA1052i provides protection against electric shocks, overvoltage, ground offset and reverse current, while significantly improving signal integrity in noisy electromagnetic environments.
By integrating an existing market accepted CAN transceiver with a Galvanic Isolator in one package, this new solution ensures matching dynamic parameters, reduces board space, improves signal performance, and increases overall reliability and cost-effectiveness.
Historically, automotive OEMs and Tier 1 suppliers have used expensive Opto Couplers to isolate the CAN transceiver, with performance in such a standalone solution tending to degrade over time.
The TJA1052i is well-suited for the growing market of hybrid and full electric vehicles (H/EVs), where high and low voltage levels co-exist. H/EVs are equipped with multiple battery modules – typically controlled via CAN by the Battery Management System – which together can supply up to 500 Volts and also power other high-voltage applications such as inverter, start/stop, DC/DC converter, charger and air conditioning systems.
These systems need to communicate with other electronic control units (ECUs) via the CAN Bus, and are typically operated from the 12V board net.
Isolated CAN products are also needed in industrial applications where ECUs controlling high voltage applications and other ECUs need to be connected to each other via the CAN bus. Application examples for the TJA1052i in non-automotive areas are industrial equipment, energy storage systems, building automation and H/EV charging stations.
“The TJA1052i is another great example of NXP’s strategy to both connect the car and improve energy efficiency – even under challenging conditions,” said Toni Versluijs, VP and GM, in-vehicle networking business, NXP Semiconductors.
“Our third-generation automotive CAN transceivers are already approved and used by multiple OEMs. By integrating galvanic isolation into the TJA1052i, we are first in the industry to deliver an automotive-grade solution that saves both space and money, while making it easier for our customers to build and connect their ECUs.”
The TJA1052i is ramping up in production with immediate effect.
Geniatech selects Entropic's silicon to power new generation of USB bus-powered MoCA adapters
CHINA: Entropic announced that its Multimedia over Coax Alliance (MoCA) silicon and software was selected by Geniatech, a leading OEM/ODM to develop a USB bus-powered MoCA adapter solution for TVs and consumer electronics (CE) devices.
MoCA is already the de-facto home networking technology used by North American Pay-TV operators. Entropic is expanding MoCA's use into European, Latin American and Asian CE markets by driving innovation with a focus on delivering a superior user experience on any networked TV platform.
Geniatech's new USB bus-powered MoCA-to-Ethernet Adapter easily connects service provider or CE devices to the MoCA backbone providing Ethernet-grade connectivity without the need for a separate
power supply or to the need to pull new CAT-5 (category 5) wiring throughout the home.
As the only semiconductor company that has developed a USB bus-powered MoCA adapter reference design, Entropic is enabling OEMs/ODMs to bring innovative MoCA-based USB solutions to market. The small form factor and low power makes possible an out-of-sight, simple installation and enables MoCA home networking to be added to any Ethernet-ready CE device or set-top-box (STB) already deployed in a consumer's home.
After installation, the MoCA backbone can be used to deliver smooth HD video from over-the-top (OTT) services, enable multi-room DVR (MR-DVR) solutions or simply distribute broadband service to other parts of the home.
MoCA is already the de-facto home networking technology used by North American Pay-TV operators. Entropic is expanding MoCA's use into European, Latin American and Asian CE markets by driving innovation with a focus on delivering a superior user experience on any networked TV platform.
Geniatech's new USB bus-powered MoCA-to-Ethernet Adapter easily connects service provider or CE devices to the MoCA backbone providing Ethernet-grade connectivity without the need for a separate
power supply or to the need to pull new CAT-5 (category 5) wiring throughout the home.
As the only semiconductor company that has developed a USB bus-powered MoCA adapter reference design, Entropic is enabling OEMs/ODMs to bring innovative MoCA-based USB solutions to market. The small form factor and low power makes possible an out-of-sight, simple installation and enables MoCA home networking to be added to any Ethernet-ready CE device or set-top-box (STB) already deployed in a consumer's home.
After installation, the MoCA backbone can be used to deliver smooth HD video from over-the-top (OTT) services, enable multi-room DVR (MR-DVR) solutions or simply distribute broadband service to other parts of the home.
Thursday, March 21, 2013
DELTA Microelectronics to expand global activities with ChipStart
DENMARK, CANADA & USA: ChipStart LLC, a leading provider of semiconductor intellectual property (SIP), and DELTA Microelectronics, a leader in ASIC services for the semiconductor industry, are partnering to bring the power of innovation to the market through a joint relationship.
The relationship will involve the sale, marketing and global representation of DELTA’s design services, including its production and test capabilities through ChipStart’s extensive sales channel.
“We are extremely pleased to be in a position to take advantage of DELTA’s intimate knowledge of the mobile payment, RFID and sensor markets and to be able to offer their extensive portfolio of solutions,” said Howard Pakosh, president and CEO, ChipStart. “By officially recognizing this partnership, we are continuing to grow our capabilities and services giving our customers the tools necessary to develop next generation technologies.”
“DELTA Microelectronics is happy to team with ChipStart. Their portfolio is complementary to DELTA’s, so we expect that our customers can gain significant synergies from this cooperation,” comments DELTA’s VP of Sales and Marketing, Gert Jørgensen.
ChipStart will promote DELTA Microelectronics’ ASIC Design Services to system houses and semiconductor communities throughout North America, with the specific focus on chips used in the areas of mobile payment systems, RFID, optical systems and sensor systems.
The relationship will involve the sale, marketing and global representation of DELTA’s design services, including its production and test capabilities through ChipStart’s extensive sales channel.
“We are extremely pleased to be in a position to take advantage of DELTA’s intimate knowledge of the mobile payment, RFID and sensor markets and to be able to offer their extensive portfolio of solutions,” said Howard Pakosh, president and CEO, ChipStart. “By officially recognizing this partnership, we are continuing to grow our capabilities and services giving our customers the tools necessary to develop next generation technologies.”
“DELTA Microelectronics is happy to team with ChipStart. Their portfolio is complementary to DELTA’s, so we expect that our customers can gain significant synergies from this cooperation,” comments DELTA’s VP of Sales and Marketing, Gert Jørgensen.
ChipStart will promote DELTA Microelectronics’ ASIC Design Services to system houses and semiconductor communities throughout North America, with the specific focus on chips used in the areas of mobile payment systems, RFID, optical systems and sensor systems.
ARM and Synopsys to deliver optimized reference implementations for ARM processors
USA & ENGLAND: ARM and Synopsys announced the availability of optimized 28-nanometer (nm) Synopsys Reference Implementations for ARM Cortex-A15 MPCore and Cortex-A7 MPCore processor clusters as well as the CoreLink CCI-400 cache-coherent interconnect.
The companies collaborated to deliver these optimized implementations in TSMC 28HPM process technology using the Synopsys Galaxy Implementation Platform, ARM Artisan standard cells and memories, and ARM POP technology for core-hardening acceleration specifically optimized for Cortex-A15 and Cortex-A7 processor implementations.
System-on-a-chip (SoC) designers can use these Reference Implementations to create high-performance Cortex-A15 and energy-efficient Cortex-A7 processor clusters, and can combine them with the CCI-400 interconnect to create a big.LITTLE processing system that delivers increased product functionality with longer battery life.
"With a diverse range of products expected in today's end markets, ARM Powered solutions need to be optimized across a spectrum of energy-efficiency and high-performance targets," said Tom Cronk, executive VP and GM, Processor Division at ARM.
"The companies' collaboration has resulted in the Synopsys Reference Implementations for Cortex-A15 and Cortex-A7 processors. They will enable our customers to more quickly converge on their aggressive design goals, and take advantage of the benefits of big.LITTLE processing and POP IP to address the demands of their target markets."
Configured for ARM Cortex-A15 and Cortex-A7 processors as well as CCI-400 interconnect, the Synopsys Reference Implementations provide tool scripts, a baseline floorplan, design constraints and documentation to serve as an optimized starting point for implementation.
These scripts, built on the widely-used Synopsys tool Reference Methodologies (RMs) and optimized for high-performance cores, leverage Galaxy Platform capabilities such as Design Compiler Graphical physical guidance for improved timing and post-route correlation.
The scripts also leverage IC Compiler technologies, including final-stage leakage recovery for reduced leakage power, data flow analysis for faster floorplan creation and transparent interface optimization for faster top-level closure. They are configured for TSMC 28HPM process technology with ARM Artisan standard cells, memories and ARM POP technology. Designers may further optimize the scripts for their own design goals, processor configurations, process technologies and libraries.
Reference Implementation technology plug-ins for the Synopsys Lynx Design System will enable a full, chip-level production design flow. Synopsys also provides expert professional services to help designers deploy and customize the Reference Implementations to achieve their specific SoC design goals.
The Synopsys Reference Implementation for the Cortex-A7 processor cluster is for a quad-core MPCore configuration, optimized first for energy efficiency, then for maximum speed to provide energy-efficient multi-processing. For high-performance multi-processing within a tight power envelope, the Reference Implementation for the Cortex-A15 processor cluster targets a dual-core configuration, optimized first for performance, then for power.
The CCI-400 interconnect implementation is optimized for the combination of these two processor clusters into a big.LITTLE processing system.
ARM and Synopsys have also collaborated on a reference verification platform for Synopsys Discovery Verification IP, which supports the ARM AMBA 4 ACE protocol and CCI-400 interconnect. With this reference verification platform, verification engineers can rapidly develop highly efficient verification environments for their cache-coherent designs.
"This latest collaboration with ARM continues our long-standing tradition of creating solutions to address our mutual customers' key design challenges," said Antun Domic, senior VP and GM, Implementation Group at Synopsys.
"The Synopsys Reference Implementations for ARM Cortex-A15 and Cortex-A7 processors as well as CCI-400 interconnect take advantage of ARM and Synopsys technologies as well as our high-performance and low-power design expertise to enable designers to achieve optimized SoC performance and power targets on an accelerated timeline."
The 28nm Reference Implementation scripts and documentation for dual-core Cortex-A15 MPCore, quad-core Cortex-A7 and CCI-400 interconnect are available today for Synopsys customers under maintenance who are ARMv7 processor licensees:
Lynx technology plug-ins for these Reference Implementations are planned to be available at the end of April, 2013. The Synopsys Verification IP and Reference Platform for AMBA 4 ACE protocol and CCI-400 interconnect are available today from Synopsys.
The companies collaborated to deliver these optimized implementations in TSMC 28HPM process technology using the Synopsys Galaxy Implementation Platform, ARM Artisan standard cells and memories, and ARM POP technology for core-hardening acceleration specifically optimized for Cortex-A15 and Cortex-A7 processor implementations.
System-on-a-chip (SoC) designers can use these Reference Implementations to create high-performance Cortex-A15 and energy-efficient Cortex-A7 processor clusters, and can combine them with the CCI-400 interconnect to create a big.LITTLE processing system that delivers increased product functionality with longer battery life.
"With a diverse range of products expected in today's end markets, ARM Powered solutions need to be optimized across a spectrum of energy-efficiency and high-performance targets," said Tom Cronk, executive VP and GM, Processor Division at ARM.
"The companies' collaboration has resulted in the Synopsys Reference Implementations for Cortex-A15 and Cortex-A7 processors. They will enable our customers to more quickly converge on their aggressive design goals, and take advantage of the benefits of big.LITTLE processing and POP IP to address the demands of their target markets."
Configured for ARM Cortex-A15 and Cortex-A7 processors as well as CCI-400 interconnect, the Synopsys Reference Implementations provide tool scripts, a baseline floorplan, design constraints and documentation to serve as an optimized starting point for implementation.
These scripts, built on the widely-used Synopsys tool Reference Methodologies (RMs) and optimized for high-performance cores, leverage Galaxy Platform capabilities such as Design Compiler Graphical physical guidance for improved timing and post-route correlation.
The scripts also leverage IC Compiler technologies, including final-stage leakage recovery for reduced leakage power, data flow analysis for faster floorplan creation and transparent interface optimization for faster top-level closure. They are configured for TSMC 28HPM process technology with ARM Artisan standard cells, memories and ARM POP technology. Designers may further optimize the scripts for their own design goals, processor configurations, process technologies and libraries.
Reference Implementation technology plug-ins for the Synopsys Lynx Design System will enable a full, chip-level production design flow. Synopsys also provides expert professional services to help designers deploy and customize the Reference Implementations to achieve their specific SoC design goals.
The Synopsys Reference Implementation for the Cortex-A7 processor cluster is for a quad-core MPCore configuration, optimized first for energy efficiency, then for maximum speed to provide energy-efficient multi-processing. For high-performance multi-processing within a tight power envelope, the Reference Implementation for the Cortex-A15 processor cluster targets a dual-core configuration, optimized first for performance, then for power.
The CCI-400 interconnect implementation is optimized for the combination of these two processor clusters into a big.LITTLE processing system.
ARM and Synopsys have also collaborated on a reference verification platform for Synopsys Discovery Verification IP, which supports the ARM AMBA 4 ACE protocol and CCI-400 interconnect. With this reference verification platform, verification engineers can rapidly develop highly efficient verification environments for their cache-coherent designs.
"This latest collaboration with ARM continues our long-standing tradition of creating solutions to address our mutual customers' key design challenges," said Antun Domic, senior VP and GM, Implementation Group at Synopsys.
"The Synopsys Reference Implementations for ARM Cortex-A15 and Cortex-A7 processors as well as CCI-400 interconnect take advantage of ARM and Synopsys technologies as well as our high-performance and low-power design expertise to enable designers to achieve optimized SoC performance and power targets on an accelerated timeline."
The 28nm Reference Implementation scripts and documentation for dual-core Cortex-A15 MPCore, quad-core Cortex-A7 and CCI-400 interconnect are available today for Synopsys customers under maintenance who are ARMv7 processor licensees:
Lynx technology plug-ins for these Reference Implementations are planned to be available at the end of April, 2013. The Synopsys Verification IP and Reference Platform for AMBA 4 ACE protocol and CCI-400 interconnect are available today from Synopsys.
Ittiam announces media cloud foray
INDIA: Ittiam Systems, a leader in video technologies and multimedia systems, announced its foray into cloud media processing, in connecting the content creator and the consumer via the ubiquitous Internet.
With content becoming the primary focus of emerging workflows, Ittiam is pleased to announce a focused investment to address that market. The company’s new division, Ittiam Media Labs, will develop and deliver end-to-end workflows that enable Media Enterprises to leverage the power of the Cloud on top of the video processing expertise that Ittiam is renowned for, over the years.
Ittiam Media Labs will focus on Quality of Experience, with technology differentiation coming out of HEVC (High Efficiency Video Coding also known as H.265) processing, among the first companies to offer that technology on the Cloud. It will cater to a genre of customers:
a) niche content owner looking to monetize the content better,
b) enterprise looking to leverage the power of the Cloud to trade-off between capital and operating investments,
c) Online Video services provider focused on seamless consumer experiences and d) Telco looking to improve efficiencies in the network to provide a tangible value that comes out of a compelling workflow.
“Media in the Cloud is a natural next step for Ittiam, where we have always been focused on disruptive innovations in the media processing technologies,” said Srini Rajam, chairman and CEO of Ittiam Systems.
“We expect online video solution providers to place a premium on the efficiency of multi-format distributions, a cornerstone of online delivery to multiple screens of Internet-connected, smart devices. This is backed by the strong interest we are seeing from online video platforms and content consumption platforms looking to differentiate and move up the value chain.“
With content becoming the primary focus of emerging workflows, Ittiam is pleased to announce a focused investment to address that market. The company’s new division, Ittiam Media Labs, will develop and deliver end-to-end workflows that enable Media Enterprises to leverage the power of the Cloud on top of the video processing expertise that Ittiam is renowned for, over the years.
Ittiam Media Labs will focus on Quality of Experience, with technology differentiation coming out of HEVC (High Efficiency Video Coding also known as H.265) processing, among the first companies to offer that technology on the Cloud. It will cater to a genre of customers:
a) niche content owner looking to monetize the content better,
b) enterprise looking to leverage the power of the Cloud to trade-off between capital and operating investments,
c) Online Video services provider focused on seamless consumer experiences and d) Telco looking to improve efficiencies in the network to provide a tangible value that comes out of a compelling workflow.
“Media in the Cloud is a natural next step for Ittiam, where we have always been focused on disruptive innovations in the media processing technologies,” said Srini Rajam, chairman and CEO of Ittiam Systems.
“We expect online video solution providers to place a premium on the efficiency of multi-format distributions, a cornerstone of online delivery to multiple screens of Internet-connected, smart devices. This is backed by the strong interest we are seeing from online video platforms and content consumption platforms looking to differentiate and move up the value chain.“
Fujitsu releases 1 Mbit and 2 Mbit FRAM products
USA: Fujitsu Semiconductor America announced two new FRAM products featuring 1 Mbit and 2 Mbits of memory. The MB85RS1MT and MB85RS2MT, the largest-capacity, serial-interface FRAM products offered by Fujitsu, will be available in sample quantities at the end of March.
The MB85RS1MT and MB85RS2MT FRAMs offer features that are ideal for smart meters, industrial machinery and medical devices, including high endurance, higher writing speed, larger density and low power consumption.
The new FRAMs can support 10 trillion writing cycles, an endurance roughly 10 times greater than previous ferroelectric memories from Fujitsu and superior to other nonvolatile memories by at least a million times. Memory devices using FRAM consume 92 percent less power during writing compared to identical-capacity EEPROMs, and feature a writing speed 920 times faster.
As a single-chip solution, the new FRAM products substantially reduce component costs, mounted area, and power consumption compared to other system memory solutions that use EEPROM or SRAM and a battery for data retention. The new FRAM devices, by eliminating the need for a battery and additional memory components, simplify the design process, save board space, and reduce maintenance costs.
FRAM is a high-speed random access memory that is non-volatile, allowing data to be retained when the power is switched off. Its speed and durability enable FRAM to safely store more data than alternative solutions in the event of a sudden power failure.
The dependability of FRAM for data retention has made it the choice of global customers for factory automation equipment, measurement devices, banking terminals, and medical devices since its introduction by Fujitsu in 1999.
The MB85RS1MT and MB85RS2MT FRAMs offer features that are ideal for smart meters, industrial machinery and medical devices, including high endurance, higher writing speed, larger density and low power consumption.
The new FRAMs can support 10 trillion writing cycles, an endurance roughly 10 times greater than previous ferroelectric memories from Fujitsu and superior to other nonvolatile memories by at least a million times. Memory devices using FRAM consume 92 percent less power during writing compared to identical-capacity EEPROMs, and feature a writing speed 920 times faster.
As a single-chip solution, the new FRAM products substantially reduce component costs, mounted area, and power consumption compared to other system memory solutions that use EEPROM or SRAM and a battery for data retention. The new FRAM devices, by eliminating the need for a battery and additional memory components, simplify the design process, save board space, and reduce maintenance costs.
FRAM is a high-speed random access memory that is non-volatile, allowing data to be retained when the power is switched off. Its speed and durability enable FRAM to safely store more data than alternative solutions in the event of a sudden power failure.
The dependability of FRAM for data retention has made it the choice of global customers for factory automation equipment, measurement devices, banking terminals, and medical devices since its introduction by Fujitsu in 1999.
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