SANTA CLARA, USA: Agilent Technologies Inc. announced shipment of the latest release of its device modeling software platform, the Integrated Circuit Characterization and Analysis Program (IC-CAP).
The new IC-CAP release radically changes the way data is stored, analyzed and selected for modeling tasks, greatly increasing workflow efficiency and ensuring continued data integrity and traceability. IC-CAP’s automated measurement solution, Wafer Professional (or WaferPro), can now access a new SQL database called IC-CAP Database. Destined to become the backbone of the device modeling flow, the new database can simplify the way device modeling teams operate.
A new tool called DataPro is also integrated with IC-CAP Database. DataPro enables rapid analysis and selection of data for the final model parameter-extraction process.
An accurate description of process variations when modeling today’s advanced semiconductor processes has become a core requirement for circuit design teams. At the beginning of the modeling flow, IC-CAP WaferPro enables engineers to execute complex measurement tasks and collect high volume data for analyzing statistical trends. Writing data directly to a database simplifies data storage, improves security and maintainability, and enables complex queries to be completed extremely fast. DataPro helps identify and eliminate outlier devices/dies that show unphysical behavior or a large statistical deviation from the mean. It then performs statistical analysis on selected targets and identifies the golden and corner dies to be used for model extraction.
“As the leading provider of semiconductor device modeling solutions, we continue to innovate to improve flow efficiency and model accuracy,” said Chris Morton, device modeling business manager with Agilent EEsof EDA. “Breakthrough capabilities like IC-CAP Database and DataPro enable our customers to focus their modeling resources on the core modeling task, knowing that their data is organized and secure.”
Rapid data analysis and selection
Agilent’s new W8503 IC-CAP DataPro connects to database or file repositories. A convenient user interface let users select target data for statistical analysis. Selected targets can be either I-V curves, such as Id versus Vd or spot data, such as Vth or Idmax.
The program runs statistical analysis on the target data and calculates mean values and variances. Statistical graphics such as histograms are available to allow users to inspect data and its distribution, and identify and eliminate outliers. The software then pinpoints the golden die to be used for typical device model extraction and the corner dies to be used for corner modeling.
New IC-CAP 2012.01 features
In addition to the SQL database support and DataPro, IC-CAP 2012.01 provides new features and enhancements, such as a reduced memory print (up to 5x) to allow loading of very large data files and a driver for the new Agilent B2900A Series source/measurement unit. Existing DC analyzer instrument drivers have also been enhanced to support time-domain measurements and higher resolution.
In addition, IC-CAP 2012.01 introduces a new simplified licensing and product structure. Major changes include introduction of a new bundle, the W8500, to replace the former Modeling Suite; a new W8520 Instrument Connectivity product that includes all drivers; and the inclusion of target and corner modeling packages into all CMOS extraction packages.
Agilent IC-CAP software is a device-modeling program that delivers powerful characterization and analysis capabilities for today’s semiconductor modeling processes. Providing efficient and accurate extraction of active device and circuit model parameters, IC-CAP performs numerous modeling tasks, including instrument control, data acquisition, graphical analysis, simulation and optimization. It is used by semiconductor foundries and design houses to characterize foundry processes.
Friday, March 2, 2012
Elpida bankruptcy set to boost DRAM prices and revenue
EL SEGUNDO, USA: Elpida Memory Inc.’s move to file bankruptcy protection this week will benefit the remaining players in the dynamic random access memory (DRAM) market, reducing supply and boosting pricing and revenue in the second half of the year, according to the IHS iSuppli Memory & Storage Service,
If more than 25 percent of Elpida’s manufacturing capacity is taken offline, the global average selling price (ASP) for all DRAM shipments is projected to rise to $1.21 by the end of 2012, up 15.5 percent from $1.05 at the end of the first half of the year. Without such a reduction in capacity, pricing would rise to $1.13 at the end of the year, up just 8.5 percent from the price at the end of the first half.
Source: IHS iSuppli, USA.
“A meaningful reduction in Elpida’s manufacturing will cause the DRAM market to go into a state of undersupply, causing prices to increase,” said Mike Howard, senior principal analyst for DRAM & memory at IHS. “Shipments likely will decrease because of the Elpida bankruptcy, even though the resulting increase in revenue—driven by higher prices—will cause the market to perform better than expected in 2012. The ultimate fate of Elpida’s manufacturing assets, which remains to be decided, will be the major factor impacting pricing and revenue growth in 2012. But one thing is certain: Elpida’s bankruptcy means the remaining DRAM players can look forward to a much rosier 2012 than they did just one week ago.”
IHS conservatively estimates that 2012 DRAM revenue will exceed $30 billion, compared to the previous forecast of $24 billion. In a preview of what is likely to happen in contract prices later this year, the spot memory market reacted drastically to the news of Elpida’s bankruptcy. Spot prices for PC DRAM jumped by more than 15 percent in just one day.
Elpida declares bankruptcy
Facing more than $1 billion in imminent debt payments, Elpida filed for bankruptcy protection on February 27. While there certainly had been concern over the financial health of the ailing Japanese DRAM maker, the suddenness of the filing has caused heads to spin in the industry.
Elpida long has been one of the leading forces in the memory market and is the last remaining DRAM maker headquartered in Japan. The company’s possible demise is a remarkable development for the industry. However, Elpida’s filing for bankruptcy does not necessarily mean the end of manufacturing for the company.
Production has not ceased at its manufacturing facilities, and its engineers, salespeople, marketers and corporate strategists are hard at work on finding a path forward.
Nevertheless, the company likely will look very different on the other side of bankruptcy. Not only will the company have to deal with its massive debt load or more than $5 billion, it also must deal with the challenges of manufacturing in the high-cost regions of Japan. At an extreme, the bankruptcy could mean that Elpida’s days as a DRAM manufacturer are completely over.
“If all of Elpida’s fabs—such as its Hiroshima facility—cease making memory permanently, then the chronicallyoversaturated DRAM industry may finally reach a state of supply/demand equilibrium,” Howard noted. “While it’s unlikely that all of Elpida’s production will disappear, this development could mark a new era for the DRAM market—one marked by stronger pricing power for suppliers.”
Supply scramble
Many existing Elpida customers during the coming months will seek alternative suppliers to secure DRAM products. DRAM is a critical component for innumerable electronic devices—most prominently notebook and desktop PCs—and a shortage of supplies can prevent devices from shipping to consumers. Because of this, DRAM buyers will look to Samsung, Hynix, Micron and Nanya to provide these critical components.
While every DRAM company likely will gain market share as customers seek reliable alternative suppliers, Micron and Nanya are expected to realize the greatest gains.
Hynix and Samsung are currently the two largest DRAM suppliers. Because of this, customers likely already use them as sources. And as customers seek additional suppliers, they will be more apt to look to Micron and Nanya.
Inotera, which supplies both Micron and Nanya, and is currently operating at less than full capacity, will see its production return to full capacity as it serves Micron and Nanya’s incremental increase in demand.
Source: IHS iSuppli, USA.
If more than 25 percent of Elpida’s manufacturing capacity is taken offline, the global average selling price (ASP) for all DRAM shipments is projected to rise to $1.21 by the end of 2012, up 15.5 percent from $1.05 at the end of the first half of the year. Without such a reduction in capacity, pricing would rise to $1.13 at the end of the year, up just 8.5 percent from the price at the end of the first half.
Source: IHS iSuppli, USA.“A meaningful reduction in Elpida’s manufacturing will cause the DRAM market to go into a state of undersupply, causing prices to increase,” said Mike Howard, senior principal analyst for DRAM & memory at IHS. “Shipments likely will decrease because of the Elpida bankruptcy, even though the resulting increase in revenue—driven by higher prices—will cause the market to perform better than expected in 2012. The ultimate fate of Elpida’s manufacturing assets, which remains to be decided, will be the major factor impacting pricing and revenue growth in 2012. But one thing is certain: Elpida’s bankruptcy means the remaining DRAM players can look forward to a much rosier 2012 than they did just one week ago.”
IHS conservatively estimates that 2012 DRAM revenue will exceed $30 billion, compared to the previous forecast of $24 billion. In a preview of what is likely to happen in contract prices later this year, the spot memory market reacted drastically to the news of Elpida’s bankruptcy. Spot prices for PC DRAM jumped by more than 15 percent in just one day.
Elpida declares bankruptcy
Facing more than $1 billion in imminent debt payments, Elpida filed for bankruptcy protection on February 27. While there certainly had been concern over the financial health of the ailing Japanese DRAM maker, the suddenness of the filing has caused heads to spin in the industry.
Elpida long has been one of the leading forces in the memory market and is the last remaining DRAM maker headquartered in Japan. The company’s possible demise is a remarkable development for the industry. However, Elpida’s filing for bankruptcy does not necessarily mean the end of manufacturing for the company.
Production has not ceased at its manufacturing facilities, and its engineers, salespeople, marketers and corporate strategists are hard at work on finding a path forward.
Nevertheless, the company likely will look very different on the other side of bankruptcy. Not only will the company have to deal with its massive debt load or more than $5 billion, it also must deal with the challenges of manufacturing in the high-cost regions of Japan. At an extreme, the bankruptcy could mean that Elpida’s days as a DRAM manufacturer are completely over.
“If all of Elpida’s fabs—such as its Hiroshima facility—cease making memory permanently, then the chronicallyoversaturated DRAM industry may finally reach a state of supply/demand equilibrium,” Howard noted. “While it’s unlikely that all of Elpida’s production will disappear, this development could mark a new era for the DRAM market—one marked by stronger pricing power for suppliers.”
Supply scramble
Many existing Elpida customers during the coming months will seek alternative suppliers to secure DRAM products. DRAM is a critical component for innumerable electronic devices—most prominently notebook and desktop PCs—and a shortage of supplies can prevent devices from shipping to consumers. Because of this, DRAM buyers will look to Samsung, Hynix, Micron and Nanya to provide these critical components.
While every DRAM company likely will gain market share as customers seek reliable alternative suppliers, Micron and Nanya are expected to realize the greatest gains.
Hynix and Samsung are currently the two largest DRAM suppliers. Because of this, customers likely already use them as sources. And as customers seek additional suppliers, they will be more apt to look to Micron and Nanya.
Inotera, which supplies both Micron and Nanya, and is currently operating at less than full capacity, will see its production return to full capacity as it serves Micron and Nanya’s incremental increase in demand.
Source: IHS iSuppli, USA.
MathWorks intros HDL code generation for MATLAB
NATICK, USA: MathWorks announced HDL Coder, which automatically generates HDL code from MATLAB, allowing engineers to implement FPGA and ASIC designs from the widely used MATLAB language. MathWorks also announced HDL Verifier, which includes FPGA hardware-in-the-loop capabilities for testing FPGA and ASIC designs. With these two products, MathWorks now provides HDL code generation and verification across MATLAB and Simulink.
“Engineers everywhere use MATLAB and Simulink to design systems and algorithms,” said Tom Erkkinen, embedded applications and certification manager, MathWorks. “Now, with HDL Coder and HDL Verifier, they no longer have to manually write HDL code or test benches to develop FPGA and ASIC designs.”
HDL Coder generates portable, synthesizable VHDL and Verilog code from MATLAB functions and Simulink models that can be used for FPGA programming or ASIC prototyping and design. As a result, engineering teams can now immediately identify the best algorithm for hardware implementation. Traceability between Simulink models and generated HDL code also supports the development of high-integrity applications that adhere to DO-254 and other standards.
“HDL Coder offers integration with Xilinx ISE design suite, creating a pushbutton workflow that makes it easy for algorithm developers who use MathWorks products to target Xilinx FPGAs,” said Vin Ratford, senior VP Worldwide Marketing and Business Development, Xilinx. “This integration also provides our mutual customers access to a broad portfolio of Xilinx optimized IP from within HDL Coder that further accelerates their productivity.”
HDL Verifier now supports FPGA hardware-in-the-loop verification for Altera and Xilinx FPGA boards. HDL Verifier provides co-simulation interfaces that link MATLAB and Simulink with Cadence Incisive, Mentor Graphics ModelSim, and Questa HDL simulators. With these capabilities, engineers can rapidly verify that their HDL implementation matches their MATLAB algorithms and Simulink system specifications.
“As adoption of FPGAs continues to grow across industries, designers need a way to bridge the verification gap from system models to FPGA design,” said Vince Hu, VP of product and corporate marketing at Altera. “HDL Verifier links system models to FPGA designs and enables engineers to perform FPGA hardware-in-the-loop verification with Altera FPGAs and Simulink. This workflow shortens verification cycles and helps engineers gain greater confidence in their silicon implementations.”
HDL Coder and HDL Verifier are available immediately. The US list prices for HDL Coder start at $10,000 and the US list prices for HDL Verifier start at $3,250.
“Engineers everywhere use MATLAB and Simulink to design systems and algorithms,” said Tom Erkkinen, embedded applications and certification manager, MathWorks. “Now, with HDL Coder and HDL Verifier, they no longer have to manually write HDL code or test benches to develop FPGA and ASIC designs.”
HDL Coder generates portable, synthesizable VHDL and Verilog code from MATLAB functions and Simulink models that can be used for FPGA programming or ASIC prototyping and design. As a result, engineering teams can now immediately identify the best algorithm for hardware implementation. Traceability between Simulink models and generated HDL code also supports the development of high-integrity applications that adhere to DO-254 and other standards.
“HDL Coder offers integration with Xilinx ISE design suite, creating a pushbutton workflow that makes it easy for algorithm developers who use MathWorks products to target Xilinx FPGAs,” said Vin Ratford, senior VP Worldwide Marketing and Business Development, Xilinx. “This integration also provides our mutual customers access to a broad portfolio of Xilinx optimized IP from within HDL Coder that further accelerates their productivity.”
HDL Verifier now supports FPGA hardware-in-the-loop verification for Altera and Xilinx FPGA boards. HDL Verifier provides co-simulation interfaces that link MATLAB and Simulink with Cadence Incisive, Mentor Graphics ModelSim, and Questa HDL simulators. With these capabilities, engineers can rapidly verify that their HDL implementation matches their MATLAB algorithms and Simulink system specifications.
“As adoption of FPGAs continues to grow across industries, designers need a way to bridge the verification gap from system models to FPGA design,” said Vince Hu, VP of product and corporate marketing at Altera. “HDL Verifier links system models to FPGA designs and enables engineers to perform FPGA hardware-in-the-loop verification with Altera FPGAs and Simulink. This workflow shortens verification cycles and helps engineers gain greater confidence in their silicon implementations.”
HDL Coder and HDL Verifier are available immediately. The US list prices for HDL Coder start at $10,000 and the US list prices for HDL Verifier start at $3,250.
MathWorks announces release 2012a of MATLAB and Simulink product families
NATICK, USA: MathWorks announced Release 2012a (R2012a) of its MATLAB and Simulink product families. New in this release are the introduction of HDL Coder, which generates HDL code from either MATLAB or Simulink for prototyping and implementation on FPGAs or ASICs, and the launch of HDL Verifier, which replaces EDA Simulator Link and adds Altera FPGA hardware-in-the-loop support. R2012a also updates 77 other products, including Polyspace embedded software verification products.
For MATLAB, R2012a highlights include:
MATLAB: Unified functions for 1-D, 2-D, and 3-D numerical integration and improved performance of basic math and interpolation functions.
MATLAB Compiler: MATLAB Compiler Runtime (MCR) available for download, simplifying distribution of compiled applications and components.
Image Processing Toolbox: Automatic image registration using intensity metric optimization.
Statistics Toolbox: Enhanced interface for fitting, prediction, and plotting with linear, generalized linear, and nonlinear regression.
System Identification Toolbox: Identification of continuous-time transfer functions
MATLAB Coder: Code generation from user-defined System objects and automated generation of dynamic shared libraries.
Computer Vision System Toolbox: Viola-Jones object detection, MSER feature detection, and CAMShift tracking.
Communications System Toolbox: USRP radio support, LTE MIMO channel models, and GPU support for LDPC, turbo decoder, and other algorithms.
R2012a highlights for Simulink include:
Simulink: Ability to run models directly from Simulink on target hardware including LEGO MINDSTORMS NXT and BeagleBoard.
Embedded Coder: AUTOSAR 4.0 compatibility, reduced data copies, and linking of code generation reports with Simulink Web views.
SimMechanics: Second-generation multibody modeling and simulation technology with new 3-D visualization.
Real-Time Windows Target: Real-time execution of models in Windows using Simulink Normal mode.
Release 2012a is available immediately and is being provided to users worldwide with current subscriptions to MathWorks Software Maintenance Service for immediate installation.
For MATLAB, R2012a highlights include:
MATLAB: Unified functions for 1-D, 2-D, and 3-D numerical integration and improved performance of basic math and interpolation functions.
MATLAB Compiler: MATLAB Compiler Runtime (MCR) available for download, simplifying distribution of compiled applications and components.
Image Processing Toolbox: Automatic image registration using intensity metric optimization.
Statistics Toolbox: Enhanced interface for fitting, prediction, and plotting with linear, generalized linear, and nonlinear regression.
System Identification Toolbox: Identification of continuous-time transfer functions
MATLAB Coder: Code generation from user-defined System objects and automated generation of dynamic shared libraries.
Computer Vision System Toolbox: Viola-Jones object detection, MSER feature detection, and CAMShift tracking.
Communications System Toolbox: USRP radio support, LTE MIMO channel models, and GPU support for LDPC, turbo decoder, and other algorithms.
R2012a highlights for Simulink include:
Simulink: Ability to run models directly from Simulink on target hardware including LEGO MINDSTORMS NXT and BeagleBoard.
Embedded Coder: AUTOSAR 4.0 compatibility, reduced data copies, and linking of code generation reports with Simulink Web views.
SimMechanics: Second-generation multibody modeling and simulation technology with new 3-D visualization.
Real-Time Windows Target: Real-time execution of models in Windows using Simulink Normal mode.
Release 2012a is available immediately and is being provided to users worldwide with current subscriptions to MathWorks Software Maintenance Service for immediate installation.
Tessera to acquire camera module manufacturing assets to accelerate market introduction of next-gen technologies
SAN JOSE, USA: Tessera Technologies Inc. announced that its wholly-owned subsidiary, DigitalOptics Corp., has agreed to acquire certain assets of Vista Point Technologies, a Tier One qualified camera module manufacturing business, from Flextronics International Ltd.
DOC will pay approximately $23 million in cash, subject to certain adjustments and costs at closing, for certain assets of Flextronics’s camera module business located in Zhuhai, China, along with the equity interests of a wholly-owned foreign enterprise that will own those assets (together, the “Zhuhai Camera Module Business”). The transaction, which is expected to close in the third quarter, if not sooner, includes existing customer contracts and a lease to an approximately 135,000-square-foot facility. DOC anticipates that the business will have a capacity to manufacture approximately 50 million camera module units per year.
“The Zhuhai Camera Module Business will allow us to drive rapid market introduction of DOC’s next-generation technology in a manner that complements our existing collaborations with camera module makers. We believe our approach is the best way to address the requirements of Tier One OEM manufacturers, which require that camera modules be delivered through dual sourcing from high-volume manufacturing facilities,” said Robert A. Young, president and CEO, Tessera Technologies.
“This transaction is a critical step in our strategy of transforming DOC from an optical and image enhancement software and components business into a Tier One qualified, vertically integrated supplier of next-generation camera modules to the $9-billion market for mobile cameras,” Young continued.
“In parallel, we continue to have active discussions with multiple Tier One OEM manufacturers of mobile phones regarding our MEMS autofocus product, and remain on track to obtain a design win in the first half of 2012 and to begin high-volume manufacturing in the fourth quarter of 2012,” said Young. “We believe our disruptive MEMS autofocus technology will offer a uniquely competitive replacement for the magnetic voice coils in use today, while enabling cameras that are thinner, faster, have more accurate lens positioning and use far less battery power. Our goal is for DOC to become profitable in 2013.”
“These assets will enable DigitalOptics Corporation to significantly increase sales of the imaging technologies we’ve acquired and developed over the past five years. Our strategy is to combine our breakthrough autofocus solutions with our other proprietary technologies so that DOC will become a leading supplier of integrated camera modules in the mobile phone market,” said Bob Roohparvar, president of DigitalOptics. “The acquisition of the Tier One qualified Zhuhai Camera Module Business provides DOC with a world-class, cost competitive facility that has the necessary production capabilities for DOC to assemble camera modules in volume, and a well-trained team of engineers and manufacturing employees.”
In addition to developing technologies to enhance optical imaging – including software that helps mobile phone cameras to correct hand motion or to improve the autofocus functions – DOC has been developing its capacity to oversee the high-volume manufacturing operations required by mobile phone makers. DOC’s steps in the past year have included hiring more than a dozen executives and managers who have experience in engineering scale-up as well as in manufacturing at similar facilities.
DOC will pay approximately $23 million in cash, subject to certain adjustments and costs at closing, for certain assets of Flextronics’s camera module business located in Zhuhai, China, along with the equity interests of a wholly-owned foreign enterprise that will own those assets (together, the “Zhuhai Camera Module Business”). The transaction, which is expected to close in the third quarter, if not sooner, includes existing customer contracts and a lease to an approximately 135,000-square-foot facility. DOC anticipates that the business will have a capacity to manufacture approximately 50 million camera module units per year.
“The Zhuhai Camera Module Business will allow us to drive rapid market introduction of DOC’s next-generation technology in a manner that complements our existing collaborations with camera module makers. We believe our approach is the best way to address the requirements of Tier One OEM manufacturers, which require that camera modules be delivered through dual sourcing from high-volume manufacturing facilities,” said Robert A. Young, president and CEO, Tessera Technologies.
“This transaction is a critical step in our strategy of transforming DOC from an optical and image enhancement software and components business into a Tier One qualified, vertically integrated supplier of next-generation camera modules to the $9-billion market for mobile cameras,” Young continued.
“In parallel, we continue to have active discussions with multiple Tier One OEM manufacturers of mobile phones regarding our MEMS autofocus product, and remain on track to obtain a design win in the first half of 2012 and to begin high-volume manufacturing in the fourth quarter of 2012,” said Young. “We believe our disruptive MEMS autofocus technology will offer a uniquely competitive replacement for the magnetic voice coils in use today, while enabling cameras that are thinner, faster, have more accurate lens positioning and use far less battery power. Our goal is for DOC to become profitable in 2013.”
“These assets will enable DigitalOptics Corporation to significantly increase sales of the imaging technologies we’ve acquired and developed over the past five years. Our strategy is to combine our breakthrough autofocus solutions with our other proprietary technologies so that DOC will become a leading supplier of integrated camera modules in the mobile phone market,” said Bob Roohparvar, president of DigitalOptics. “The acquisition of the Tier One qualified Zhuhai Camera Module Business provides DOC with a world-class, cost competitive facility that has the necessary production capabilities for DOC to assemble camera modules in volume, and a well-trained team of engineers and manufacturing employees.”
In addition to developing technologies to enhance optical imaging – including software that helps mobile phone cameras to correct hand motion or to improve the autofocus functions – DOC has been developing its capacity to oversee the high-volume manufacturing operations required by mobile phone makers. DOC’s steps in the past year have included hiring more than a dozen executives and managers who have experience in engineering scale-up as well as in manufacturing at similar facilities.
NEC selects ClariPhy’s LightSpeed 40G coherent SoC
OFC/NFOEC 2012, IRVINE, USA: ClariPhy Communications Inc., a leading developer of ultra-high speed mixed signal, digital signal processing (MXSP) system-on-chip (SoC) solutions for coherent optical networks, announced that NEC Corp. has selected ClariPhy’s LightSpeed coherent SoC for integration into NEC’s optical transceiver modules. ClariPhy’s LightSpeed CL4010 SoC is the industry’s first single chip CMOS solution targeting the highly anticipated deployment of 40 gigabit per second (40G) coherent optical networks.
The rapid emergence of coherent optical transmission technology, enabled by advanced DSP-based modulation techniques, represents a paradigm shift in optical networking that promises to dramatically increase both the reach and capacity of fiber networks. ClariPhy's LightSpeed CL4010 is the world’s first application specific standard product (ASSP) for coherent optical transmission, enabling module suppliers like NEC to address the surging demand from operators for 40G coherent deployments.
The LightSpeed CL4010 offers industry leading integration and lowest power consumption compared to alternate solutions enabling standard Multi-Source Agreement (MSA) form factors from module suppliers. The LightSpeed CL4010 enables ultra-long haul transmission of more than 3,000 km, while providing a high degree of spectral efficiency critical in metro and long haul networks.
“By delivering the world’s first single chip 40G coherent ASSP we are driving an open ecosystem that will allow operators to take advantage of industry wide compatibility and superior optical performance,” said Nariman Yousefi, CEO, ClariPhy Communications Inc. “We deeply value NEC’s confidence in our technology and execution ability and are honored with the opportunity of partnering with an industry leader.”
“The single-chip integration of the LightSpeed SoC enables us to build standard form-factor optical transceiver modules with digital coherent technology,” said Tomokazu Ito, GM, Fiber Optics Devices Division, NEC. “The superior performance delivered by the LightSpeed SoC coupled with compatibility with widely deployed enhanced forward error correction solutions helps us significantly increase optical reach compared to current products.”
“The LightSpeed SoC product family enables us to leverage a single development across multiple markets and applications. ClariPhy’s ability to execute on developing and designing state of the art complex SoCs matched by industry leading service quality are key contributors to accelerating time to market for our products,” said Tetsuyuki Suzaki, senior manager for High Speed Optics, Fiber Optics Device Division, NEC, Japan.
The rapid emergence of coherent optical transmission technology, enabled by advanced DSP-based modulation techniques, represents a paradigm shift in optical networking that promises to dramatically increase both the reach and capacity of fiber networks. ClariPhy's LightSpeed CL4010 is the world’s first application specific standard product (ASSP) for coherent optical transmission, enabling module suppliers like NEC to address the surging demand from operators for 40G coherent deployments.
The LightSpeed CL4010 offers industry leading integration and lowest power consumption compared to alternate solutions enabling standard Multi-Source Agreement (MSA) form factors from module suppliers. The LightSpeed CL4010 enables ultra-long haul transmission of more than 3,000 km, while providing a high degree of spectral efficiency critical in metro and long haul networks.
“By delivering the world’s first single chip 40G coherent ASSP we are driving an open ecosystem that will allow operators to take advantage of industry wide compatibility and superior optical performance,” said Nariman Yousefi, CEO, ClariPhy Communications Inc. “We deeply value NEC’s confidence in our technology and execution ability and are honored with the opportunity of partnering with an industry leader.”
“The single-chip integration of the LightSpeed SoC enables us to build standard form-factor optical transceiver modules with digital coherent technology,” said Tomokazu Ito, GM, Fiber Optics Devices Division, NEC. “The superior performance delivered by the LightSpeed SoC coupled with compatibility with widely deployed enhanced forward error correction solutions helps us significantly increase optical reach compared to current products.”
“The LightSpeed SoC product family enables us to leverage a single development across multiple markets and applications. ClariPhy’s ability to execute on developing and designing state of the art complex SoCs matched by industry leading service quality are key contributors to accelerating time to market for our products,” said Tetsuyuki Suzaki, senior manager for High Speed Optics, Fiber Optics Device Division, NEC, Japan.
Quarter-end effect results in 5-10 percent drop for 2HFeb. mainstream NAND Flash average contract price
TAIWAN: According to DRAMeXchange, a research division of TrendForce, as Chinese New Year holiday sales were not as expected for some downstream clients, most were generally uneager towards post-holiday inventory restocking. A portion of memory card and UFD vendors are urging NAND flash suppliers to assist them with price cutting and promotional sales activity to stimulate market demand in the weak season.
Therefore, purchasing was weak on the NAND flash market in 2HFeb. Affected by the quarter-end effect, certain NAND flash suppliers adopted an aggressive price cut strategy early on to encourage downstream client purchases; thus, mainstream NAND flash average contract price fell by 5-10 percent in 2HFeb.
Source: DRAMeXchange, Taiwan.
The following three factors will be the main influences on the NAND flash market in 1H12:
1. Macroeconomically speaking, international negotiations and cooperative efforts have resulted in the gradual ease of the European sovereign debt storm as well as instability that has affected economies and financial markets worldwide. Therefore, the global economy will be back on the road to sustainable recovery in 2H12, which will help raise NAND flash end product sales and enhance the peak season effect in 2H12.
2. In terms of the supply side, although most major suppliers are suspending capacity expansion plans in response to relatively conservative macroeconomic environments in 1H12, as yields continue to be improved, new 20nm-class process output ratios will gradually increase in 2Q12. Taking system product performance and reliability requirements into consideration, in 2H12 most NAND flash suppliers will continue to introduce low cost, high capacity eMMC, mSATA, and SSD products manufactured with 20nm-class process technology.
3. As for the demand side, NAND flash end application demand is expected to be weak in 1H12, as a result of delayed economic recovery and the slow season effect. It is anticipated that only the unveiling of certain bestselling products will bring a hint of spring to the NAND flash market in the 1H12 slow season. In 2H12, related manufacturers will introduce new smartphone, tablet PC, and ultrabook models equipped with new ecosystem combinations of next-generation features such as high performance microprocessors, operating systems, wireless communication technology, high resolution images, etc. This will help increase the proportion of 20nm-class embedded NAND flash products adopted by smart mobile devices in 2H12.
In conclusion, TrendForce believes the NAND flash market will likely stay in a state of oversupply in 1H12. Affected by a mix of factors such as the quarter-end effect in 1Q, anticipation of new bestselling products hitting the market, and the traditional weak season, NAND Flash price is expected to show a mild downtrend in the short term.
Source: DRAMeXchange, Taiwan.
Therefore, purchasing was weak on the NAND flash market in 2HFeb. Affected by the quarter-end effect, certain NAND flash suppliers adopted an aggressive price cut strategy early on to encourage downstream client purchases; thus, mainstream NAND flash average contract price fell by 5-10 percent in 2HFeb.
Source: DRAMeXchange, Taiwan.The following three factors will be the main influences on the NAND flash market in 1H12:
1. Macroeconomically speaking, international negotiations and cooperative efforts have resulted in the gradual ease of the European sovereign debt storm as well as instability that has affected economies and financial markets worldwide. Therefore, the global economy will be back on the road to sustainable recovery in 2H12, which will help raise NAND flash end product sales and enhance the peak season effect in 2H12.
2. In terms of the supply side, although most major suppliers are suspending capacity expansion plans in response to relatively conservative macroeconomic environments in 1H12, as yields continue to be improved, new 20nm-class process output ratios will gradually increase in 2Q12. Taking system product performance and reliability requirements into consideration, in 2H12 most NAND flash suppliers will continue to introduce low cost, high capacity eMMC, mSATA, and SSD products manufactured with 20nm-class process technology.
3. As for the demand side, NAND flash end application demand is expected to be weak in 1H12, as a result of delayed economic recovery and the slow season effect. It is anticipated that only the unveiling of certain bestselling products will bring a hint of spring to the NAND flash market in the 1H12 slow season. In 2H12, related manufacturers will introduce new smartphone, tablet PC, and ultrabook models equipped with new ecosystem combinations of next-generation features such as high performance microprocessors, operating systems, wireless communication technology, high resolution images, etc. This will help increase the proportion of 20nm-class embedded NAND flash products adopted by smart mobile devices in 2H12.
In conclusion, TrendForce believes the NAND flash market will likely stay in a state of oversupply in 1H12. Affected by a mix of factors such as the quarter-end effect in 1Q, anticipation of new bestselling products hitting the market, and the traditional weak season, NAND Flash price is expected to show a mild downtrend in the short term.
Source: DRAMeXchange, Taiwan.
Calypto delivers bus interface libraries to easily connect high level synthesis models to ARM platform
SANTA CLARA, USA: Calypto Design Systems Inc., the leader in Electronic System Level (ESL) hardware design and Register Transfer Level (RTL) power optimization, announced bus interface libraries that connect hardware subsystems implemented with Calypto’s High Level Synthesis product (HLS), Catapult Synthesis, with AMBA AXI bus interfaces.
The libraries include master and slave interfaces with both Transaction Level Modeling (TLM) and HLS views, which allows easy interplay between a TLM 2.0 platform and HLS implementation flow without degrading simulation performance or hardware quality. The highly parameterizable AXI interface supports a wide range of configurations including burst modes, bus width and auxiliary control signals.
“The AXI interfaces are the first in a series of libraries in development at Calypto that will make Catapult C more readily available to mainstream designers," said Shawn McCloud, VP of Marketing at Calypto. “They are written entirely in SystemC and tuned through the Catapult C synthesis tool. These interfaces are a great example of the benefits of mixing cycle accurate SystemC for control with abstract SystemC/C++ to implement a hardware subsystem.”
The AXI interface library is tuned so the resulting hardware is optimized for the user’s specific performance requirements, configuration mode and target technology. Availability in April, please contact Calypto Sales for specific pricing and information.
The libraries include master and slave interfaces with both Transaction Level Modeling (TLM) and HLS views, which allows easy interplay between a TLM 2.0 platform and HLS implementation flow without degrading simulation performance or hardware quality. The highly parameterizable AXI interface supports a wide range of configurations including burst modes, bus width and auxiliary control signals.
“The AXI interfaces are the first in a series of libraries in development at Calypto that will make Catapult C more readily available to mainstream designers," said Shawn McCloud, VP of Marketing at Calypto. “They are written entirely in SystemC and tuned through the Catapult C synthesis tool. These interfaces are a great example of the benefits of mixing cycle accurate SystemC for control with abstract SystemC/C++ to implement a hardware subsystem.”
The AXI interface library is tuned so the resulting hardware is optimized for the user’s specific performance requirements, configuration mode and target technology. Availability in April, please contact Calypto Sales for specific pricing and information.
FSI International receives follow-on orders for ANTARES Systems from leading global device manufacturer
MINNEAPOLIS, USA: FSI International Inc. announced that a leading global device producer has placed follow-on orders for its ANTARES CryoKinetic Cleaning System. The chip provider currently uses the ANTARES System for various particle removal processes and with these orders, is adding capacity for advanced technology generations. The systems are expected to ship in fiscal 2012.*
The ANTARES System is a fully automated, single-wafer, CryoKinetic system used for processing 200/300mm wafers with capabilities to remove nanoscale particles. CryoKinetic processing technology is an all-dry, chemical free process that removes particles through impact by high-velocity cryogenic Ar/N2 aerosol, and reduces defects without damaging the wafer surface, even on copper and porous low-k films.
The system’s highly efficient dry cleaning solution can be used for a variety of particle removal applications in FEOL and BEOL. Many of the leading logic device manufacturers worldwide utilize the ANTARES® System for its defect reduction and yield improvement benefits at 32/28nm and above technology nodes.
The ANTARES System is a fully automated, single-wafer, CryoKinetic system used for processing 200/300mm wafers with capabilities to remove nanoscale particles. CryoKinetic processing technology is an all-dry, chemical free process that removes particles through impact by high-velocity cryogenic Ar/N2 aerosol, and reduces defects without damaging the wafer surface, even on copper and porous low-k films.
The system’s highly efficient dry cleaning solution can be used for a variety of particle removal applications in FEOL and BEOL. Many of the leading logic device manufacturers worldwide utilize the ANTARES® System for its defect reduction and yield improvement benefits at 32/28nm and above technology nodes.
Thursday, March 1, 2012
Luxtera and ST to enable high-volume silicon photonics solutions
GENEVA, SWITZERLAND & CARLSBAD, USA: STMicroelectronics and Luxtera Inc., a leader in silicon photonics, announced a new agreement to bring Luxtera’s leading-edge IP and knowledge in silicon photonics to a dedicated process to be developed by ST at its 300mm facility in Crolles, France. Production at ST’s Crolles site will enable the two companies to support the market with the world’s most advanced low-cost, high-volume solution for silicon photonics components and systems.
Silicon photonics is regarded as a key enabler of future very high-speed computing and communications applications such as optical networking, CPU interconnect, and data storage, as they scale to multi-terabit connectivity. The technology allows high-speed optical communications devices to be built using well-proven, low-cost silicon manufacturing technology, rather than more expensive compound semiconductor materials containing gallium or indium.
Flavio Benetti, GM of mixed process division at STMicroelectronics, said: “The powerful synergy of this partnership, derived from the complementary strengths of two technology and industry leaders, represents a tremendous breakthrough. This will bring silicon photonics into the mainstream of important technologies such as optical networking, ultra-fast computer processors and other applications via the commercial volume availability of a best-in-class silicon photonics IP platform.”
With this collaboration ST has been granted the rights to use the Luxtera’s silicon photonics technology that will be implemented in the new ST photonics process and its future generations. ST will provide Luxtera with a reliable, scalable, and cost-effective supply chain, allowing Luxtera to satisfy its growing market in terms of volume and quality requirements. Working together the companies will bring silicon photonics into a new era, enabling it to become a cost-effective mainstream technology.
“Luxtera has found a broad market opportunity for silicon photonics that requires an expanded supply chain and continued technology advancement. We can now offer our customers a high-volume, capable source of supply and an aggressive long-term photonic process technology roadmap. This will advance our base technology and enable the integration of optical transceivers with SoCs from advanced CMOS nodes to deliver photonic-enabled SoCs for large scale systems. In turn, ST can now offer customers the world’s leading optical IP as the two companies expand the silicon photonics ecosystem,” said Greg Young, president and CEO of Luxtera.
The new advanced 300mm silicon photonics platform being developed by ST will offer these key benefits:
Performance: Scalability of low-cost transceivers for data rates of 100Gb, 400Gb and upwards;
Density: Ultra-high-density interconnect with the lowest power consumption;
Interoperability: with support for 1310nm, 1490nm and 1550nm wavelengths.
The optimized silicon photonics process will be developed at ST’s Crolles technology center in France, where ST’s other major CMOS R&D programs, including the value-added derivative high-performance analog BiCMOS technologies, are running.
Silicon photonics is regarded as a key enabler of future very high-speed computing and communications applications such as optical networking, CPU interconnect, and data storage, as they scale to multi-terabit connectivity. The technology allows high-speed optical communications devices to be built using well-proven, low-cost silicon manufacturing technology, rather than more expensive compound semiconductor materials containing gallium or indium.
Flavio Benetti, GM of mixed process division at STMicroelectronics, said: “The powerful synergy of this partnership, derived from the complementary strengths of two technology and industry leaders, represents a tremendous breakthrough. This will bring silicon photonics into the mainstream of important technologies such as optical networking, ultra-fast computer processors and other applications via the commercial volume availability of a best-in-class silicon photonics IP platform.”
With this collaboration ST has been granted the rights to use the Luxtera’s silicon photonics technology that will be implemented in the new ST photonics process and its future generations. ST will provide Luxtera with a reliable, scalable, and cost-effective supply chain, allowing Luxtera to satisfy its growing market in terms of volume and quality requirements. Working together the companies will bring silicon photonics into a new era, enabling it to become a cost-effective mainstream technology.
“Luxtera has found a broad market opportunity for silicon photonics that requires an expanded supply chain and continued technology advancement. We can now offer our customers a high-volume, capable source of supply and an aggressive long-term photonic process technology roadmap. This will advance our base technology and enable the integration of optical transceivers with SoCs from advanced CMOS nodes to deliver photonic-enabled SoCs for large scale systems. In turn, ST can now offer customers the world’s leading optical IP as the two companies expand the silicon photonics ecosystem,” said Greg Young, president and CEO of Luxtera.
The new advanced 300mm silicon photonics platform being developed by ST will offer these key benefits:
Performance: Scalability of low-cost transceivers for data rates of 100Gb, 400Gb and upwards;
Density: Ultra-high-density interconnect with the lowest power consumption;
Interoperability: with support for 1310nm, 1490nm and 1550nm wavelengths.
The optimized silicon photonics process will be developed at ST’s Crolles technology center in France, where ST’s other major CMOS R&D programs, including the value-added derivative high-performance analog BiCMOS technologies, are running.
Samsung DFM ready for 20nm based on Mentor Graphics Calibre platform
WILSONVILLE, USA: Mentor Graphics Corp. announced that Samsung Electronics and Mentor have successfully delivered a complete design-for-manufacturing (DFM) sign-off reference solution for Samsung’s foundry customers based on the Calibre platform. The DFM sign-off solution is available for world-class consumer and telecommunications designs targeting advanced process nodes. Samsung has already released the Calibre kits to their customers for 32 nm and 28 nm, and has completed evaluation for 20nm.
“We have been working closely with Mentor to provide a comprehensive and consistent ecosystem for our customers,” said Kee Sup Kim, VP of Infrastructure Design Center, Samsung Electronics. “We have used Mentor’s 32/28 nm DFM solution on several advanced SoCs to reduce late-stage problems that could lead to delayed product releases or slower-than-expected yield ramp-up. We are currently working with Mentor to expand the DFM solution to 20 nm processes as well.”
The components of the Calibre DFM platform at Samsung include the Calibre LFD product for litho simulation and hot spot pattern identification; the Calibre nmDRC and Calibre PM products for pattern-based design rule and hot spot checking and fixing; and the Calibre YieldAnalyzer product, which is used in conjunction with the Samsung manufacturing analysis deck for DFM scoring and critical area analysis (CAA).
“At advanced nodes, proper incorporation of DFM techniques can create a competitive edge for both foundries and fabless designers,” said Joseph Sawicki, VP and GM for Design-to-Silicon Division at Mentor Graphics. “We are pleased to be working with Samsung on the Calibre platform to provide this competitive edge to our mutual customers.”
“We have been working closely with Mentor to provide a comprehensive and consistent ecosystem for our customers,” said Kee Sup Kim, VP of Infrastructure Design Center, Samsung Electronics. “We have used Mentor’s 32/28 nm DFM solution on several advanced SoCs to reduce late-stage problems that could lead to delayed product releases or slower-than-expected yield ramp-up. We are currently working with Mentor to expand the DFM solution to 20 nm processes as well.”
The components of the Calibre DFM platform at Samsung include the Calibre LFD product for litho simulation and hot spot pattern identification; the Calibre nmDRC and Calibre PM products for pattern-based design rule and hot spot checking and fixing; and the Calibre YieldAnalyzer product, which is used in conjunction with the Samsung manufacturing analysis deck for DFM scoring and critical area analysis (CAA).
“At advanced nodes, proper incorporation of DFM techniques can create a competitive edge for both foundries and fabless designers,” said Joseph Sawicki, VP and GM for Design-to-Silicon Division at Mentor Graphics. “We are pleased to be working with Samsung on the Calibre platform to provide this competitive edge to our mutual customers.”
Tokyo Tech installs EV Group wafer cleaning system
TOKYO, JAPAN: EV Group (EVG), a leading supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, has shipped an EVG301 semi-automated single-wafer cleaning system to Tokyo Institute of Technology (Tokyo Tech).
The EVG301 has already been installed at Tokyo Tech's Arai-Nishiyama Lab, and is being used in the research and development of advanced optical communication ICs. Specifically, the EVG 301 is being leveraged by Tokyo Tech to remove particles from the surfaces of pre-bonded III-V compound semiconductor and silicon-on-insulator (SOI) wafers that are used in the production of optical ICs.
As network traffic continues to rise dramatically, the need for higher levels of integration in optical communication ICs, including the use of optical routers and wave division multiplexing (WDM) transceivers, is needed to keep transmission rates of each channel at manageable levels. In response to this need, Tokyo Tech's Arai-Nishiyama lab initiated work to develop compound semiconductor-based optical transceiver components on silicon, which enables higher levels of circuit integration. EVG's EVG301 megasonic wafer cleaning system was accepted and installed by Tokyo Tech to help accelerate this project.
Dr. Nobuhiko Nishiyama, associate professor at Arai-Nishiyama Lab, commented: "When you build optical circuits on a silicon platform, creating high-quality luminescent components is essential, and improving wafer bond quality plays an important role in making this happen. The existence of even very small particles creates voids on the wafer bonding interface, and such voids prohibit the normal performance of luminescent components. The EVG301 megasonic wafer cleaning system by EV Group completely removes such particles and enables perfect bonding results. I am confident our research will show significant progress with the use of this technology."
Today's electronics industry is built on high-speed/high-integration silicon devices. Integration of optical circuits on silicon not only improves network speed, but also increases the functionality of IC devices, including membrane photonic integrated circuits. Effective stacking of III-V compound semiconductors, such as indium phosphide (InP) and gallium indium arsenide phosphide (GaInAsP), to create high-performance optical ICs on silicon is essential to enabling such higher integration and functionality. Wafer cleaning technology, offered by EV Group, removes voids caused by particles during the wafer bonding process.
"It is our pleasure to have our EVG301 accepted by Tokyo Tech, which leads optical communication IC research and development," stated Yuichi Otsuka, representative director of EV Group Japan KK. "The EVG301 is widely used in research organizations as the de facto standard for wafer cleaning for various wafer bonding processes—and it is offered as a standard component to EVG's leading-edge, fully integrated wafer bonding systems. Tokyo Tech's selection of the EVG301 for use in their Arai-Nishiyama Lab for advanced research in high-performance semiconductor lasers and highly integrated optical ICs reaffirms the system's status as the tool of record in this field of research."
The EVG301 has already been installed at Tokyo Tech's Arai-Nishiyama Lab, and is being used in the research and development of advanced optical communication ICs. Specifically, the EVG 301 is being leveraged by Tokyo Tech to remove particles from the surfaces of pre-bonded III-V compound semiconductor and silicon-on-insulator (SOI) wafers that are used in the production of optical ICs.
As network traffic continues to rise dramatically, the need for higher levels of integration in optical communication ICs, including the use of optical routers and wave division multiplexing (WDM) transceivers, is needed to keep transmission rates of each channel at manageable levels. In response to this need, Tokyo Tech's Arai-Nishiyama lab initiated work to develop compound semiconductor-based optical transceiver components on silicon, which enables higher levels of circuit integration. EVG's EVG301 megasonic wafer cleaning system was accepted and installed by Tokyo Tech to help accelerate this project.
Dr. Nobuhiko Nishiyama, associate professor at Arai-Nishiyama Lab, commented: "When you build optical circuits on a silicon platform, creating high-quality luminescent components is essential, and improving wafer bond quality plays an important role in making this happen. The existence of even very small particles creates voids on the wafer bonding interface, and such voids prohibit the normal performance of luminescent components. The EVG301 megasonic wafer cleaning system by EV Group completely removes such particles and enables perfect bonding results. I am confident our research will show significant progress with the use of this technology."
Today's electronics industry is built on high-speed/high-integration silicon devices. Integration of optical circuits on silicon not only improves network speed, but also increases the functionality of IC devices, including membrane photonic integrated circuits. Effective stacking of III-V compound semiconductors, such as indium phosphide (InP) and gallium indium arsenide phosphide (GaInAsP), to create high-performance optical ICs on silicon is essential to enabling such higher integration and functionality. Wafer cleaning technology, offered by EV Group, removes voids caused by particles during the wafer bonding process.
"It is our pleasure to have our EVG301 accepted by Tokyo Tech, which leads optical communication IC research and development," stated Yuichi Otsuka, representative director of EV Group Japan KK. "The EVG301 is widely used in research organizations as the de facto standard for wafer cleaning for various wafer bonding processes—and it is offered as a standard component to EVG's leading-edge, fully integrated wafer bonding systems. Tokyo Tech's selection of the EVG301 for use in their Arai-Nishiyama Lab for advanced research in high-performance semiconductor lasers and highly integrated optical ICs reaffirms the system's status as the tool of record in this field of research."
Subscribe to:
Posts (Atom)
