BANGALORE, INDIA: NXP has announced the appointment of Dr. Sankara Narayan as Vice President and Country Manager for NXP in India. In this role, Dr. Narayan will be responsible for managing and growing NXP’s India operations. Additionally, he will also focus on engaging with local industry and academia to develop customized applications to cater to the Indian market.
Dr. Narayan started his career with Philips Research in The Netherlands and has 26 years of rich industry experience. He joined Philips Semiconductors (which in 2006became NXP Semiconductors) in 1993 to handle global technology development and coordination. In this role, he was also responsible for establishing European governmental and university relations for joint technology development of CMOS/BiCMOS processes. In the last decade, he has been in charge for global quality and sustainability management for NXP.
“We are very pleased to have Dr. Narayan join NXP India team. His wealth of knowledge and his team of R&D professionals will greatly benefit NXP in the region and will help us continue to bring High Performance Mixed Signal (HPMS) technology products to the benefit of emerging markets in the region,” said Rene Penning de Vries, CTO, NXP.
"India as a market presents tremendous opportunities for us across sectors. Moving forward, we envision our R&D centre to take over complete ownership of end-to-end product development,” said Dr. Sankara Narayan, VP and country manager, NXP India. “I'm truly excited to be a part of the NXP India team at this stage and look forward to taking India operations to scale newer heights.”
Outgoing India head of NXP, Neeraj Paliwal’s is moving to NXP Hamburg to take on new responsibility as the VP Engineering, Business Unit Identification at NXP Semiconductors. In his new role, Neeraj will manage BU Identification global R&D teams located in Germany, Austria, France, Belgium, Netherlands, and India.
Tuesday, November 29, 2011
Mindspeed ships five millionth multi-core packet processor for CPE
NEWPORT BEACH, USA: Mindspeed Technologies Inc., a leading supplier of semiconductor solutions for network infrastructure applications, has shipped five million Comcerto multi-core system-on-chip (SoC) embedded packet processors for customer premises equipment (CPE), including residential gateways and broadband home routers (BHRs).
“Our Comcerto 1000 processor has particularly strong penetration in the BHR market, where we are playing an important role in this segment’s rapid expansion and evolution,” said Naser Adas, VP and GM, CPE and wireless, at Mindspeed.
“We continue to deliver a growing range of capabilities on the multi-core SoC foundation of our Comcerto processor, which combines performance with extremely low power consumption and carrier-class voice, quality of service (QoS) and reliability. This architecture has proven ideal for value-added services deployment by enabling remotely-managed applications from carriers, or third-party providers, to be run on one core, while the other remains dedicated to primary gateway functionality including voice processing and IPTV routing.”
Mindspeed recently extended its Comcerto 1000 family to enable a new category of CPE service offload platform (SOP) hardware that can be used with existing BHRs in the connected home. SOP Boxes will make it easier and more cost-effective for service providers to partner with best-of-breed home automation, utility monitoring, security, healthcare and networked appliance vendors to deliver cloud-based applications that can be provisioned and securely managed using their current hardware and software infrastructure.
“The broadband home networking market is on the rise, as new devices and technologies allow consumers to turn their homes into digital hubs for media sharing, social networking, and a wide variety of emerging value-added, carrier-managed broadband health, energy and security services,” said Jeff Heynen, directing analyst for broadband access at Infonetics Research. “Next generation residential broadband home routers have become the fastest growing segment of the broadband customer premises equipment devices market."
“Our Comcerto 1000 processor has particularly strong penetration in the BHR market, where we are playing an important role in this segment’s rapid expansion and evolution,” said Naser Adas, VP and GM, CPE and wireless, at Mindspeed.
“We continue to deliver a growing range of capabilities on the multi-core SoC foundation of our Comcerto processor, which combines performance with extremely low power consumption and carrier-class voice, quality of service (QoS) and reliability. This architecture has proven ideal for value-added services deployment by enabling remotely-managed applications from carriers, or third-party providers, to be run on one core, while the other remains dedicated to primary gateway functionality including voice processing and IPTV routing.”
Mindspeed recently extended its Comcerto 1000 family to enable a new category of CPE service offload platform (SOP) hardware that can be used with existing BHRs in the connected home. SOP Boxes will make it easier and more cost-effective for service providers to partner with best-of-breed home automation, utility monitoring, security, healthcare and networked appliance vendors to deliver cloud-based applications that can be provisioned and securely managed using their current hardware and software infrastructure.
“The broadband home networking market is on the rise, as new devices and technologies allow consumers to turn their homes into digital hubs for media sharing, social networking, and a wide variety of emerging value-added, carrier-managed broadband health, energy and security services,” said Jeff Heynen, directing analyst for broadband access at Infonetics Research. “Next generation residential broadband home routers have become the fastest growing segment of the broadband customer premises equipment devices market."
Magma’s Tekton achieves adoption milestone
SAN JOSE, USA: Magma Design Automation Inc. announced that since its release 18 months ago, Tekton has grown its customer base to more than 25 companies, achieving the fastest adoption rate of any tool in the company’s history.
Tekton, the most advanced sign-off-quality static timing analysis (STA) tool on the market, was introduced to the industry in the spring of 2010. This unprecedented growth was accomplished despite the chip industry’s shrinking electronic design automation (EDA) budgets and designers’ historical unwillingness to change sign-off tools.
“Tekton has garnered strong customer interest for multiple reasons,” said Jacob Avidan, general manager of Magma’s Digital Sign-Off Business Unit. “First and foremost, the need for faster runtimes and true multi-mode, multi-corner (MMMC) sign-off is not being met by legacy tools today. Second, Tekton’s superior architecture, which was designed specifically for multi-core processing and concurrent MMMC analysis, has been proven on production designs. And third, customer confidence is high in Magma’s ability to sustain its performance and technology leadership in timing sign-off solutions.”
Customers are using Tekton to accelerate post place-and-route engineering change order (ECO) loops as well as for final sign-off runs. With the slow runtimes of legacy tools and the increasing number of scenarios that need to be analyzed, today’s timing closure phase can take two to three months to complete.
Tekton’s concurrent MMMC analysis and multi-threaded architecture can save tens – if not hundreds – of hours over the span of numerous ECO loops. Tekton also provides a huge savings in hardware costs for MMMC analysis. Recent customer results show savings between 75 and 95 percent of machine-count usage for running large numbers of scenarios. With fast and sign-off-accurate results in the ECO flow, customers can have confidence in using Tekton for final timing sign-off analysis and eliminate the need for additional STA point tools.
Tekton’s customers range from the largest networking and mobile broadband design houses to some of the world’s largest semiconductor manufacturers. More than half of the top 20 IDMs and fabless semiconductor companies are committed to using Tekton.
“The diversity of customers using Tekton has driven our R&D and support resources to produce a robust tool that works across a broad range of design styles and technology nodes including advanced nodes such as 28 and 20 nanometer. This diversity has also driven continued development to maintain Tekton’s competitive edge over other STA tools,” Avidan added. “In the last 9 months alone, Tekton’s runtime has been improved by over 2X while maintaining the same sign-off accuracy.”
Tekton was developed as part of a fully integrated system that includes extraction sign-off and place-and-route capabilities that use the same data base and are MMMC aware. This allows the platform engines to work simultaneously and to achieve higher quality of results and throughput compared to competitive point-tool solutions.
Tekton, the most advanced sign-off-quality static timing analysis (STA) tool on the market, was introduced to the industry in the spring of 2010. This unprecedented growth was accomplished despite the chip industry’s shrinking electronic design automation (EDA) budgets and designers’ historical unwillingness to change sign-off tools.
“Tekton has garnered strong customer interest for multiple reasons,” said Jacob Avidan, general manager of Magma’s Digital Sign-Off Business Unit. “First and foremost, the need for faster runtimes and true multi-mode, multi-corner (MMMC) sign-off is not being met by legacy tools today. Second, Tekton’s superior architecture, which was designed specifically for multi-core processing and concurrent MMMC analysis, has been proven on production designs. And third, customer confidence is high in Magma’s ability to sustain its performance and technology leadership in timing sign-off solutions.”
Customers are using Tekton to accelerate post place-and-route engineering change order (ECO) loops as well as for final sign-off runs. With the slow runtimes of legacy tools and the increasing number of scenarios that need to be analyzed, today’s timing closure phase can take two to three months to complete.
Tekton’s concurrent MMMC analysis and multi-threaded architecture can save tens – if not hundreds – of hours over the span of numerous ECO loops. Tekton also provides a huge savings in hardware costs for MMMC analysis. Recent customer results show savings between 75 and 95 percent of machine-count usage for running large numbers of scenarios. With fast and sign-off-accurate results in the ECO flow, customers can have confidence in using Tekton for final timing sign-off analysis and eliminate the need for additional STA point tools.
Tekton’s customers range from the largest networking and mobile broadband design houses to some of the world’s largest semiconductor manufacturers. More than half of the top 20 IDMs and fabless semiconductor companies are committed to using Tekton.
“The diversity of customers using Tekton has driven our R&D and support resources to produce a robust tool that works across a broad range of design styles and technology nodes including advanced nodes such as 28 and 20 nanometer. This diversity has also driven continued development to maintain Tekton’s competitive edge over other STA tools,” Avidan added. “In the last 9 months alone, Tekton’s runtime has been improved by over 2X while maintaining the same sign-off accuracy.”
Tekton was developed as part of a fully integrated system that includes extraction sign-off and place-and-route capabilities that use the same data base and are MMMC aware. This allows the platform engines to work simultaneously and to achieve higher quality of results and throughput compared to competitive point-tool solutions.
Global Unichip's USB 3.0 device controller IP passes USB-IF test procedure for SuperSpeed products
HSINCHU, TAIWAN: Global Unichip Corp. (GUC), the Flexible ASIC Leader, announced that its USB 3.0 Device Controller IP has passed the USB-IF Test Procedure for SuperSpeed products and is now listed in the Integrator List.
The USB 3.0 Device Controller IP supports SuperSpeed USB peripheral functionality that provides a 10x data transfer rate over Hi-Speed USB. It is backward compatible with USB 2.0 to ensure interoperability with billions of USB products already on the market.
GUC's USB 3.0 Device Controller IP is highly configurable and employs an aggressive power saving methodology. It is compatible with USB 3.0 PHYs, including GUC's own USB 3.0 PHY IP, through a standard PIPE interface. GUC's USB 3.0 PHY IP is currently under silicon characterization and expects to pass the complete USB-IF test by the first quarter of 2012.
The new USB 3.0 Device Controller IP is the latest addition to GUC's library of high quality digital, analog and mixed-signal IP. With GUC's silicon-proven USB 3.0 IP, designers can achieve reduced design time and guaranteed quality when developing products for advanced computing, entertainment, and networking applications.
"Our goal is to provide today's designers with the a broad custom and third party IP portfolio that includes the specific macros they need to bring their next innovative idea to reality," said Dr. Jen-Tai Hsu, senior director of Engineering, GUC."
The USB 3.0 Device Controller IP supports SuperSpeed USB peripheral functionality that provides a 10x data transfer rate over Hi-Speed USB. It is backward compatible with USB 2.0 to ensure interoperability with billions of USB products already on the market.
GUC's USB 3.0 Device Controller IP is highly configurable and employs an aggressive power saving methodology. It is compatible with USB 3.0 PHYs, including GUC's own USB 3.0 PHY IP, through a standard PIPE interface. GUC's USB 3.0 PHY IP is currently under silicon characterization and expects to pass the complete USB-IF test by the first quarter of 2012.
The new USB 3.0 Device Controller IP is the latest addition to GUC's library of high quality digital, analog and mixed-signal IP. With GUC's silicon-proven USB 3.0 IP, designers can achieve reduced design time and guaranteed quality when developing products for advanced computing, entertainment, and networking applications.
"Our goal is to provide today's designers with the a broad custom and third party IP portfolio that includes the specific macros they need to bring their next innovative idea to reality," said Dr. Jen-Tai Hsu, senior director of Engineering, GUC."
SpringSoft targets chip finishing apps with new Laker Blitz
HSINCHU, TAIWAN: SpringSoft Inc., a global supplier of specialized IC design software, announced the immediate availability of the Laker Blitz chip-level layout editor, a new software product targeting chip finishing applications and the latest addition to its popular family of Laker custom IC design and layout automation solutions.
The Laker Blitz product enables high-speed viewing and editing of chip-level layouts to streamline tapeout-to-manufacturing operations. It is ideally suited for designs with massive data sets, such as advanced-node system-on-chip (SoC) implementations and large memory chips that are widely used in consumer electronics.
Chip finishing is one of the last physical design steps before manufacturing and generally requires engineers to merge large design files, run design rule checks (DRC), and make final corrections, all while under enormous schedule pressures. Currently, they most likely use layout tools or viewers that have been optimized for other tasks and have limited performance or minimal editing capabilities.
By contrast, SpringSoft’s Blitz software is specifically optimized for speed and user productivity during the chip finishing part of the design cycle, in keeping with the company’s focus on providing specialized solutions that address key pain points in the chip development process. It loads and exports GDSII data files 5 to 20 times faster than conventional layout tools, offers more robust layout editing capabilities than most high-capacity layout viewers, and provides an extensive library of Tool Command Language (Tcl) extensions for automating data manipulation.
Semiconductor manufacturers, foundries and fabless design companies are using SpringSoft’s new Laker offering for a variety of chip finishing applications, including IP merging, SoC assembly, and chip-level DRC reviews.
“There is a tools gap today when it comes to finishing a chip. Conventional layout editors are too slow, mask viewers are cumbersome with little or no editing capabilities, and DRC tools are limited in scope,” said Dave Reed, senior director of marketing for custom IC design solutions at SpringSoft. “Laker Blitz brings together performance, capacity, and proven layout technologies to significantly reduce the time and effort required to achieve final tapeout of high quality, high-density chip designs.”
The Laker Blitz product enables high-speed viewing and editing of chip-level layouts to streamline tapeout-to-manufacturing operations. It is ideally suited for designs with massive data sets, such as advanced-node system-on-chip (SoC) implementations and large memory chips that are widely used in consumer electronics.
Chip finishing is one of the last physical design steps before manufacturing and generally requires engineers to merge large design files, run design rule checks (DRC), and make final corrections, all while under enormous schedule pressures. Currently, they most likely use layout tools or viewers that have been optimized for other tasks and have limited performance or minimal editing capabilities.
By contrast, SpringSoft’s Blitz software is specifically optimized for speed and user productivity during the chip finishing part of the design cycle, in keeping with the company’s focus on providing specialized solutions that address key pain points in the chip development process. It loads and exports GDSII data files 5 to 20 times faster than conventional layout tools, offers more robust layout editing capabilities than most high-capacity layout viewers, and provides an extensive library of Tool Command Language (Tcl) extensions for automating data manipulation.
Semiconductor manufacturers, foundries and fabless design companies are using SpringSoft’s new Laker offering for a variety of chip finishing applications, including IP merging, SoC assembly, and chip-level DRC reviews.
“There is a tools gap today when it comes to finishing a chip. Conventional layout editors are too slow, mask viewers are cumbersome with little or no editing capabilities, and DRC tools are limited in scope,” said Dave Reed, senior director of marketing for custom IC design solutions at SpringSoft. “Laker Blitz brings together performance, capacity, and proven layout technologies to significantly reduce the time and effort required to achieve final tapeout of high quality, high-density chip designs.”
Magma’s Titan delivers higher quality and faster design convergence for analog IP
SAN JOSE, USA: Magma Design Automation announced the availability of a new release of the Titan Analog/Mixed-Signal (Titan AMS) Design Platform. With patent-pending analog design technology, Titan provides an innovative FlexCell-to-GDSII analog/mixed-signal (AMS) flow that organically integrates both electrical design and physical design into one unified design methodology.
This paradigm-shifting, electrical-physical co-design flow ranges from front-end design such as schematics to circuit optimization in Titan Analog Design Accelerator (Titan ADX) to back-end design such as placement and routing in Titan Analog Virtual Prototyper (Titan AVP) and Titan Shape-Based Router (Titan SBR). Leveraging tight integration through a unified database and enhanced algorithms Titan further accelerates AMS design and reuse, setting a new standard in design automation for productivity, portability and quality.
This new Titan release supports Magma’s Silicon One initiative by providing faster design convergence, larger capacity and highly automated design flows that address the increasing size, complexity, and shortened development cycles, of today’s AMS designs.
Key enhancements include updates to foundry partner AMS reference flows, more efficient legacy data format support through native OpenAccess (OA) support, embedding Magma’s super-fast FineSim SPICE circuit simulation for faster and more efficient process modeling, the addition of several new advanced FlexCells that serve as process-independent analog building blocks, support of higher frequency transistor characteristics for RF design, increased capacity to simultaneously handle hundreds of multi-corner scenarios, parallel optimization through distributed implementation for faster runtime and better quality of results (QoR), and tight integration with Magma’s digital implementation tool Talus for more efficient top-level routing and chip finishing. Titan’s enhanced co-design flow has proven its value for early adopters who have experienced 2X improvement in design productivity while achieving better results.
“As evidenced by initial successes by and Panasonic, iWatt and Exar as well as recent achievements by Fujitsu and other users, Titan is experiencing very rapid adoption for a wide variety of analog designs being manufactured in process nodes ranging from 180 to 28 nanometer and below,” said Anirudh Devgan, GM of Magma’s Custom Design Business Unit. “More than half of the top 20 semiconductor companies in the world are Titan customers and several more are actively evaluating this technology. This growth is a direct result of Titan’s advanced analog circuit design capabilities, such as non-linear constraint-based circuit optimization and high capacity and high quality analog routing that allow Titan to offer significant quality and turnaround-time advantages over traditional analog design and implementation tools. Backed by Magma’s talented engineering, R&D and worldwide FAE teams, new customers can be confident in adopting this innovative solution.”
This paradigm-shifting, electrical-physical co-design flow ranges from front-end design such as schematics to circuit optimization in Titan Analog Design Accelerator (Titan ADX) to back-end design such as placement and routing in Titan Analog Virtual Prototyper (Titan AVP) and Titan Shape-Based Router (Titan SBR). Leveraging tight integration through a unified database and enhanced algorithms Titan further accelerates AMS design and reuse, setting a new standard in design automation for productivity, portability and quality.
This new Titan release supports Magma’s Silicon One initiative by providing faster design convergence, larger capacity and highly automated design flows that address the increasing size, complexity, and shortened development cycles, of today’s AMS designs.
Key enhancements include updates to foundry partner AMS reference flows, more efficient legacy data format support through native OpenAccess (OA) support, embedding Magma’s super-fast FineSim SPICE circuit simulation for faster and more efficient process modeling, the addition of several new advanced FlexCells that serve as process-independent analog building blocks, support of higher frequency transistor characteristics for RF design, increased capacity to simultaneously handle hundreds of multi-corner scenarios, parallel optimization through distributed implementation for faster runtime and better quality of results (QoR), and tight integration with Magma’s digital implementation tool Talus for more efficient top-level routing and chip finishing. Titan’s enhanced co-design flow has proven its value for early adopters who have experienced 2X improvement in design productivity while achieving better results.
“As evidenced by initial successes by and Panasonic, iWatt and Exar as well as recent achievements by Fujitsu and other users, Titan is experiencing very rapid adoption for a wide variety of analog designs being manufactured in process nodes ranging from 180 to 28 nanometer and below,” said Anirudh Devgan, GM of Magma’s Custom Design Business Unit. “More than half of the top 20 semiconductor companies in the world are Titan customers and several more are actively evaluating this technology. This growth is a direct result of Titan’s advanced analog circuit design capabilities, such as non-linear constraint-based circuit optimization and high capacity and high quality analog routing that allow Titan to offer significant quality and turnaround-time advantages over traditional analog design and implementation tools. Backed by Magma’s talented engineering, R&D and worldwide FAE teams, new customers can be confident in adopting this innovative solution.”
Mitsubishi Electric develops C-band GaN high-electron mobility transistors for satellite earth stations
TOKYO, JAPAN: Mitsubishi Electric Corp. has developed two Gallium Nitride (GaN) High-Electron Mobility Transistor (HEMT) C-band (4–8GHz) amplifiers for satellite earth stations. The MGFC50G5867 and MGFC47G5867, featuring power outputs of an industry-leading 100W and 50W, respectively, will ship on a sample basis beginning January 10, 2012.
Gallium Arsenide (GaAs) amplifiers have been commonly employed in microwave power transmitters. In recent years, however, Gallium Nitride (GaN) amplifiers have become increasingly popular due to their high breakdown-voltage and power density, high saturated electron speed and ability to contribute to power saving and the downsizing of power transmitter equipment.
Mitsubishi Electric first began sample shipments of high-output GaN HEMT amplifiers for C-band space application in March 2010.
Gallium Arsenide (GaAs) amplifiers have been commonly employed in microwave power transmitters. In recent years, however, Gallium Nitride (GaN) amplifiers have become increasingly popular due to their high breakdown-voltage and power density, high saturated electron speed and ability to contribute to power saving and the downsizing of power transmitter equipment.
Mitsubishi Electric first began sample shipments of high-output GaN HEMT amplifiers for C-band space application in March 2010.
Anritsu and AWR expand AWR Connected for Anritsu
EL SEGUNDO, USA: AWR Corp., the innovation leader in high-frequency EDA software, and Anritsu Corp., a global provider of test and measurement solutions, announced the expansion of AWR Connected for Anritsu.
The initial AWR Connected for Anritsu offering consisted of AWR’s Microwave Office software and Anritsu’s VectorStar vector signal network analyzers and was announced in January 2009; however today’s news expands this to team Anritsu’s MS269xA/MS2830A Signal Analyzer series and MS269xA-002/MS2830A-02x Vector Signal Generator Option (SA/VSG) hardware with AWR’s Visual System Simulator (VSS) communications system design software.
AWR’s VSS software is a block-diagram based system simulator targeted at radar and communications system design. Combining simulation software and measurements with measurement instrumentation from Anritsu benefits communication systems designers such that complex, digitally modulated test signals (LTE, WiMAX, GSM/Edge) used to drive end hardware tests via Anritsu’s SA/VSG can now be assured that they are the same as those used throughout the design cycle within the VSS software.
Additionally, AWR Connected for Anritsu SA/VSG provides a comprehensive solution of simulation software and measurement instruments that address component design through to end-to-end communication systems and gives designers a competitive edge by reducing cost and time to market.
The initial AWR Connected for Anritsu offering consisted of AWR’s Microwave Office software and Anritsu’s VectorStar vector signal network analyzers and was announced in January 2009; however today’s news expands this to team Anritsu’s MS269xA/MS2830A Signal Analyzer series and MS269xA-002/MS2830A-02x Vector Signal Generator Option (SA/VSG) hardware with AWR’s Visual System Simulator (VSS) communications system design software.
AWR’s VSS software is a block-diagram based system simulator targeted at radar and communications system design. Combining simulation software and measurements with measurement instrumentation from Anritsu benefits communication systems designers such that complex, digitally modulated test signals (LTE, WiMAX, GSM/Edge) used to drive end hardware tests via Anritsu’s SA/VSG can now be assured that they are the same as those used throughout the design cycle within the VSS software.
Additionally, AWR Connected for Anritsu SA/VSG provides a comprehensive solution of simulation software and measurement instruments that address component design through to end-to-end communication systems and gives designers a competitive edge by reducing cost and time to market.
Impressive growth continues for tablet computers
SCOTTSDALE, USA: Perhaps the most-watched system trend in personal computing today is the meteoric growth of the touch-screen tablet computers, which have become a major force in the large consumer market for portable computers that run multimedia applications and connect wirelessly to the Internet.
In 2011, total personal computer units (including tablets) is forecast to climb to 414 million systems worldwide, which would be a 13 percent increase over 366 million in 2010 (see figure). However, if tablet computers are excluded from the market total, PC unit shipments are expected to grow by only a little more than 1 percent in 2011 to 353 million systems compared to 349 million in 2010.
Source: IC Insights, USA.
Sales of touch-screen tablets are accelerating the overall growth in portable computers, but these systems are also cutting into consumer purchases of standard keyboard-operated notebooks—especially netbooks, which briefly fueled portable PC shipments several years ago. Worldwide purchases of touch-screen tablet computers are expected to increase at a CAGR of 81 percent between 2010 and 2015, while standard notebook PCs (including netbooks) are forecast to grow an annual average rate of slightly more than 7 percent in this time period.
The sharp upswing in tablet sales is undercutting growth of standard PCs. The look and feel of tablets, along with slick marketing campaigns by Apple and competitors, has convinced a growing number of consumers to buy touch-screen systems instead of new standard notebooks. In many cases, touch-screen tablets are not completely replacing the home PC, but they are delaying purchases of new notebooks and desktop computers.
Keyboard computers, still, are needed by most PC users because they are better suited for certain tasks--such as typing regular-length documents or e-mails, working on spreadsheets, or creating new multimedia content. IC Insights believes about one quarter of the 2011 tablets were bought by consumers in lieu of notebooks, and that percent is expected to grow to about one third in next few years. It is still believed that most homes will still need at least one standard PC to handle all computing applications in the future.
In 2011, total personal computer units (including tablets) is forecast to climb to 414 million systems worldwide, which would be a 13 percent increase over 366 million in 2010 (see figure). However, if tablet computers are excluded from the market total, PC unit shipments are expected to grow by only a little more than 1 percent in 2011 to 353 million systems compared to 349 million in 2010.
Source: IC Insights, USA.Sales of touch-screen tablets are accelerating the overall growth in portable computers, but these systems are also cutting into consumer purchases of standard keyboard-operated notebooks—especially netbooks, which briefly fueled portable PC shipments several years ago. Worldwide purchases of touch-screen tablet computers are expected to increase at a CAGR of 81 percent between 2010 and 2015, while standard notebook PCs (including netbooks) are forecast to grow an annual average rate of slightly more than 7 percent in this time period.
The sharp upswing in tablet sales is undercutting growth of standard PCs. The look and feel of tablets, along with slick marketing campaigns by Apple and competitors, has convinced a growing number of consumers to buy touch-screen systems instead of new standard notebooks. In many cases, touch-screen tablets are not completely replacing the home PC, but they are delaying purchases of new notebooks and desktop computers.
Keyboard computers, still, are needed by most PC users because they are better suited for certain tasks--such as typing regular-length documents or e-mails, working on spreadsheets, or creating new multimedia content. IC Insights believes about one quarter of the 2011 tablets were bought by consumers in lieu of notebooks, and that percent is expected to grow to about one third in next few years. It is still believed that most homes will still need at least one standard PC to handle all computing applications in the future.
IAR Systems eases software development for Renesas SH-based embedded systems
STOCKHOLM, SWEDEN: IAR Systems announced the availability of version 2.20 of IAR Embedded Workbench for SH. The new product version is an important addition to IAR Systems broad portfolio of C and C++ tools for building and debugging embedded system software for Renesas MCUs.
The new version of IAR Embedded Workbench for SH includes new optimizations and new powerful debugger functionality as well as integration with Subversion, one of the most popular version control systems on the market.
The compiler has been improved to optimize for higher execution speed, compared to the previous version. These improvements include options for more aggressive loop unrolling and function inlining. Developers of C++ applications can now also benefit from Virtual Function Elimination (VFE), where unused virtual functions are removed during the build process, resulting in tighter object code.
The IAR C-SPY Debugger is an important part of the integrated development environment for SH. The simulator version of the debugger includes a new Timeline window allowing graphically correlated visualization of the call stack and the interrupt log, both plotted against time. This view provides a clear view of the system’s basic behavior.
The E10A-USB emulator version of the IAR C-SPY Debugger provides new functionality. Support for software breakpoints is now included and it is also possible to set breakpoints during program execution. The profiling tool can now present statistics based on trace data of the application’s performance.
An increasingly high number of 32-bit designs are RTOS-based and IAR Embedded Workbench for SH now comes with thread-safe libraries, allowing safe execution of multiple threads at the same time.
IAR Embedded Workbench provides full support for SH-2A/ SH-2A FPU devices, a popular choice both in the automotive industry and in industrial automation. Version 2.20 contains support for the latest SH devices from Renesas.
The co-operation between IAR Systems and Renesas Electronics started in the mid-1980ies and IAR Systems today provides the most comprehensive tool support in the industry for Renesas 8-, 16-, and 32-bit devices.
The new version of IAR Embedded Workbench for SH includes new optimizations and new powerful debugger functionality as well as integration with Subversion, one of the most popular version control systems on the market.
The compiler has been improved to optimize for higher execution speed, compared to the previous version. These improvements include options for more aggressive loop unrolling and function inlining. Developers of C++ applications can now also benefit from Virtual Function Elimination (VFE), where unused virtual functions are removed during the build process, resulting in tighter object code.
The IAR C-SPY Debugger is an important part of the integrated development environment for SH. The simulator version of the debugger includes a new Timeline window allowing graphically correlated visualization of the call stack and the interrupt log, both plotted against time. This view provides a clear view of the system’s basic behavior.
The E10A-USB emulator version of the IAR C-SPY Debugger provides new functionality. Support for software breakpoints is now included and it is also possible to set breakpoints during program execution. The profiling tool can now present statistics based on trace data of the application’s performance.
An increasingly high number of 32-bit designs are RTOS-based and IAR Embedded Workbench for SH now comes with thread-safe libraries, allowing safe execution of multiple threads at the same time.
IAR Embedded Workbench provides full support for SH-2A/ SH-2A FPU devices, a popular choice both in the automotive industry and in industrial automation. Version 2.20 contains support for the latest SH devices from Renesas.
The co-operation between IAR Systems and Renesas Electronics started in the mid-1980ies and IAR Systems today provides the most comprehensive tool support in the industry for Renesas 8-, 16-, and 32-bit devices.
Monday, November 28, 2011
Cymer reduces chipmakers' operating costs with next gen iGLX
SAN DIEGO, USA: Cymer Inc., the world's leading supplier of light sources used by chipmakers to pattern advanced semiconductor chips, announced its third-generation Gas Lifetime eXtension (iGLX) control system for Argon Fluoride (ArF) immersion light sources.
An exclusive offering for chipmakers with OnPulse, the value-added feature is an improvement over previous generations of gas management systems, and is designed to double gas lifetime and automate gas optimization to eliminate manual intervention between service events.
At high-utilization sites, iGLX can provide up to an additional nine to 16 hours productivity per light source each year. As an additional benefit, iGLX also reduces the consumption of fluorine gas by up to 20 percent, while maintaining existing light source performance and enhancing environmentally-friendly manufacturing.
"Chipmakers continue to demand increased tool availability and iGLX offers higher uptime and enables increased wafer output," said Ed Brown, president and chief operating officer of Cymer. "iGLX is another example of Cymer's ongoing commitment to continuous improvement and bringing increased value to chipmaker customers through our widely-adopted OnPulse offerings."
iGLX is currently available to OnPulse customers on ArF immersion light sources as a field upgrade.
An exclusive offering for chipmakers with OnPulse, the value-added feature is an improvement over previous generations of gas management systems, and is designed to double gas lifetime and automate gas optimization to eliminate manual intervention between service events.
At high-utilization sites, iGLX can provide up to an additional nine to 16 hours productivity per light source each year. As an additional benefit, iGLX also reduces the consumption of fluorine gas by up to 20 percent, while maintaining existing light source performance and enhancing environmentally-friendly manufacturing.
"Chipmakers continue to demand increased tool availability and iGLX offers higher uptime and enables increased wafer output," said Ed Brown, president and chief operating officer of Cymer. "iGLX is another example of Cymer's ongoing commitment to continuous improvement and bringing increased value to chipmaker customers through our widely-adopted OnPulse offerings."
iGLX is currently available to OnPulse customers on ArF immersion light sources as a field upgrade.
Analog Devices’ 16-channel audio D/A converter provides high-performance audio at lower power
NORWOOD, USA: Analog Devices Inc. (ADI) introduced a 16-channel audio D/A converter today capable of improving audio system performance and reducing power consumption for professional, “prosumer” and automotive audio equipment applications.
The 24-bit ADAU1966 16-channel audio D/A converter provides 118dB SNR (signal-to-noise ratio) performance at 32 kHz to 192 kHz sampling rates. Its 118 dB SNR performance is achieved with a lowest in class power consumption of less than 300 mW for 16-channel operation by running the digital portion of the ADAU1966 at a lower voltage. The digital supply can be generated on chip via a linear regulator allowing the ADAU1966 to operate off a single analog supply. Alternatively, the regulator can be bypassed and a separate 2.5V to 3.3V supply provided to the chip.
Operating the ADAU1966 with full-scale differential output voltage of 3 Vrms reduces the need for downstream gain and preserves a high SNR against electrically-coupled system noise. By using the ADAU1966 A/D converter’s on-board PLL (phase-locked loop) to derive the internal master clock from an external left/right clock, the ADAU1966 eliminates the need for a separate high frequency master clock and can be used with or without a bit clock.
The ADAU1966 is qualified for AEC-100 automotive applications and operates at a -40° C to +105° C temperature range. It also features an SPI/I2C port which allows an external microcontroller to adjust volume and read the chip temperature to within +/-3°C.
The 24-bit ADAU1966 16-channel audio D/A converter provides 118dB SNR (signal-to-noise ratio) performance at 32 kHz to 192 kHz sampling rates. Its 118 dB SNR performance is achieved with a lowest in class power consumption of less than 300 mW for 16-channel operation by running the digital portion of the ADAU1966 at a lower voltage. The digital supply can be generated on chip via a linear regulator allowing the ADAU1966 to operate off a single analog supply. Alternatively, the regulator can be bypassed and a separate 2.5V to 3.3V supply provided to the chip.
Operating the ADAU1966 with full-scale differential output voltage of 3 Vrms reduces the need for downstream gain and preserves a high SNR against electrically-coupled system noise. By using the ADAU1966 A/D converter’s on-board PLL (phase-locked loop) to derive the internal master clock from an external left/right clock, the ADAU1966 eliminates the need for a separate high frequency master clock and can be used with or without a bit clock.
The ADAU1966 is qualified for AEC-100 automotive applications and operates at a -40° C to +105° C temperature range. It also features an SPI/I2C port which allows an external microcontroller to adjust volume and read the chip temperature to within +/-3°C.
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