GENEVA, SWITZERLAND: Following the successful launch of its advanced STM32F4 ARM Cortex-M4 microcontroller family, STMicroelectronics has begun shipping the STM32F4 Discovery Kit to appointed distributors worldwide. The kit provides an ultra low-cost development environment enabling fast, convenient design starts using the new devices.
The STM32F4 Discovery Kit builds on ST's proven formula, established with its sub-$10 USB plug-in Discovery Kits for the STM8S/L and STM32L/VL families. The kit includes a board featuring the STM32F407VGT6 microcontroller and circuitry to speed up development of applications utilizing the microcontroller's signal-processing capability and innovative peripherals. The board includes a MEMS motion sensor for functions such as movement and gesture detection, a MEMS digital microphone plus audio DAC with class-D speaker driver, pushbuttons, indicator LEDs and a USB micro-A/B connector for USB OTG connectivity.
The kit embeds the STLINK/V2 for rapid debugging and programming and is compatible with third-party Integrated Design Environments (IDEs) such as Atollic TrueSTUDIO, IAR EWARM, Keil MDK-ARM and Tasking VX-Toolset. It can also be used with IAR and Keil free-of-charge distributions for designs with code size up to 32KB and Atollic TrueSTUDIO Lite, which has no limitations on code size or usage time.
In addition, the kit provides a large library of sample code for actions such as audio playback and recording firmware upgrade from an USB key, interacting with the system watchdog, and using the microcontroller's low-power modes. Sample software demonstrating the MEMS motion-sensing capability is also pre-loaded in on-board Flash.
"The STM32F4 Discovery Kit includes everything required for beginners and experienced users to start new designs quickly," said Michel Buffa, GM of STMicroelectronics' Microcontroller Division. "Over 120,000 discovery kits for STM8 and STM32 microcontrollers are now in the field, and we have already shipped more than 10,000 units of the STM32F4 Discovery Kit. I expect demand to grow as developers look to the STM32F4 family for increased performance and feature integration."
ST announced the STM32F4 microcontroller family, the world's highest performance Cortex-M product with 210DMIPS/363 Coremark at 168MHz – comprising the STM32F405, STM32F407, STM32F415 and STM32F417 series - in September 2011. The new devices extend ST's STM32 platform to include over 250 pin- and software-compatible devices, and enable developers to leverage the advanced signal-processing capabilities and increased speed of the ARM Cortex-M4 processor with Floating Point Unit (FPU).
Compared to existing ARM Cortex-M3 based STM32 variants, the family provides access to extra, innovative peripherals including a parallel camera interface supporting data speeds up to 54 Mbytes/s, dedicated audio features including a PLL and full-duplex I2S, and up to 15 communication interfaces such as SPI, SDIO, CAN and up to two USB OTG ports.
The STM32F415 and STM32F417 also integrate a crypto/hash processor providing hardware acceleration for AES 128, 192, 256, Triple DES, and HASH (MD5, SHA-1), in addition to the CRC calculation unit and analog true Random Number Generator featured on all STM32F4 devices. Family members also share power-saving innovations such as dynamic power scaling, an enhanced low-power RTC, and efficient 90nm CMOS process technology.
Friday, October 28, 2011
ARM discloses technical details of next version of ARM architecture
SANTA CLARA, USA: ARM disclosed technical details of its new ARMv8 architecture, the first ARM architecture to include a 64-bit instruction set. ARMv8 broadens the ARM architecture to embrace 64-bit processing and extends virtual addressing, building on the rich heritage of the 32-bit ARMv7 architecture upon which market leading cores such as the Cortex-A9 and Cortex-A15 processors are built.
The ARM architecture is unique in its ability to span the full range of electronic devices and equipment, from tiny sensors through to large scale infrastructure equipment. Building on the industry standard 32-bit ARM architecture, the new ARMv8 architecture will expand the reach of ARM processor-based solutions into consumer and enterprise applications where extended virtual addressing and 64-bit data processing are required.
The ARMv8 architecture consists of two main execution states, AArch64 and AArch32. The AArch64 execution state introduces a new instruction set, A64 for 64-bit processing. The AArch32 state supports the existing ARM instruction set. The key features of the current ARMv7 architecture, including TrustZone, virtualization and NEON advanced SIMD, are maintained or extended in the ARMv8 architecture.
“With our increasingly connected world, the market for 32-bit processing continues to expand and evolve creating new opportunities for 32-bit ARMv7 based processors in embedded, real-time and open application platforms,” said Mike Muller, CTO, ARM. “We believe the ARMv8 architecture is ideally suited to enable the ARM partnership to continue to grow in 32-bit application spaces and bring diverse, innovative and energy-efficient solutions to 64-bit processing markets.”
In support of the introduction of the ARMv8 architecture, ARM is working to ensure a robust design ecosystem to support the 64-bit instruction set. The ARM compiler and Fast Models with ARMv8 support have already been made available to key ecosystem partners. Initial support for a range of open source operating systems, applications and third-party tools is already in development. Working together the ARM partnership is collaborating to accelerate development of a 64-bit ecosystem, in many cases as a natural extension to the broad ecosystem in place to support ARMv7 based devices in the market today.
"ARM is an important partner for Microsoft," said KD Hallman, general manager, Microsoft Corp. "The evolution of ARM to support a 64-bit architecture is a significant development for ARM and for the ARM ecosystem. We look forward to witnessing this technology's potential to enhance future ARM-based solutions."
“The combination of NVIDIA’s leadership in energy-efficient, high-performance processing and the new ARMv8 architecture will enable game-shifting breakthroughs in devices across the full range of computing – from smartphones through to supercomputers,” said Dan Vivoli, senior VP, NVIDIA.
“The current growth trajectory of data centers, driven by the viral explosion of social media and cloud computing, will continue to accelerate. The ability to handle this data increase with energy-efficient solutions is vital,” said Vinay Ravuri, VP and GM of AppliedMicro’s Processor Business Unit. “The ARM 64-bit architecture provides the right balance of performance, efficiency and cost to scale to meet these growing demands and we are very excited to be a leading partner in implementing solutions based on the ARMv8 architecture.”
The ARMv8 architecture will enable the development of ARM architecture compatible devices that can be designed to maximize the benefits across both 32-bit and 64-bit application areas. This will bring the advantages of energy-efficient 64-bit computing to new applications such as high-end servers and computing, as well as offering backwards compatibility and migration for existing software through a consistent architecture.
The ARMv8 architecture specifications describing all aspects of the ARMv8 architecture are available now to partners under license. ARM will disclose processors based on ARMv8 during 2012, with consumer and enterprise prototype systems expected in 2014.
The ARM architecture is unique in its ability to span the full range of electronic devices and equipment, from tiny sensors through to large scale infrastructure equipment. Building on the industry standard 32-bit ARM architecture, the new ARMv8 architecture will expand the reach of ARM processor-based solutions into consumer and enterprise applications where extended virtual addressing and 64-bit data processing are required.
The ARMv8 architecture consists of two main execution states, AArch64 and AArch32. The AArch64 execution state introduces a new instruction set, A64 for 64-bit processing. The AArch32 state supports the existing ARM instruction set. The key features of the current ARMv7 architecture, including TrustZone, virtualization and NEON advanced SIMD, are maintained or extended in the ARMv8 architecture.
“With our increasingly connected world, the market for 32-bit processing continues to expand and evolve creating new opportunities for 32-bit ARMv7 based processors in embedded, real-time and open application platforms,” said Mike Muller, CTO, ARM. “We believe the ARMv8 architecture is ideally suited to enable the ARM partnership to continue to grow in 32-bit application spaces and bring diverse, innovative and energy-efficient solutions to 64-bit processing markets.”
In support of the introduction of the ARMv8 architecture, ARM is working to ensure a robust design ecosystem to support the 64-bit instruction set. The ARM compiler and Fast Models with ARMv8 support have already been made available to key ecosystem partners. Initial support for a range of open source operating systems, applications and third-party tools is already in development. Working together the ARM partnership is collaborating to accelerate development of a 64-bit ecosystem, in many cases as a natural extension to the broad ecosystem in place to support ARMv7 based devices in the market today.
"ARM is an important partner for Microsoft," said KD Hallman, general manager, Microsoft Corp. "The evolution of ARM to support a 64-bit architecture is a significant development for ARM and for the ARM ecosystem. We look forward to witnessing this technology's potential to enhance future ARM-based solutions."
“The combination of NVIDIA’s leadership in energy-efficient, high-performance processing and the new ARMv8 architecture will enable game-shifting breakthroughs in devices across the full range of computing – from smartphones through to supercomputers,” said Dan Vivoli, senior VP, NVIDIA.
“The current growth trajectory of data centers, driven by the viral explosion of social media and cloud computing, will continue to accelerate. The ability to handle this data increase with energy-efficient solutions is vital,” said Vinay Ravuri, VP and GM of AppliedMicro’s Processor Business Unit. “The ARM 64-bit architecture provides the right balance of performance, efficiency and cost to scale to meet these growing demands and we are very excited to be a leading partner in implementing solutions based on the ARMv8 architecture.”
The ARMv8 architecture will enable the development of ARM architecture compatible devices that can be designed to maximize the benefits across both 32-bit and 64-bit application areas. This will bring the advantages of energy-efficient 64-bit computing to new applications such as high-end servers and computing, as well as offering backwards compatibility and migration for existing software through a consistent architecture.
The ARMv8 architecture specifications describing all aspects of the ARMv8 architecture are available now to partners under license. ARM will disclose processors based on ARMv8 during 2012, with consumer and enterprise prototype systems expected in 2014.
Thursday, October 27, 2011
ACM Research Shanghai launches ultra iSFP polishing platform
SHANGHAI, CHINA: ACM Research Shanghai Ltd has introduced its newest semiconductor manufacturing platform, the integrated Ultra iSFP. The tool performs damage-free 65nm to 45nm copper (Cu) interconnect stress free polishing (SFP).
It integrates the electrochemical mechanism of SFP with ultra low down force chemical mechanical planarization (ULCMP) and thermal flow etch (TFE) to take advantage of the specific benefits of each process step, while ensuring there is no damage to the underlying device structure.
Using the Ultra iSFP to form SiO2 based air gap interconnect structures offers several advantages. Its process is simple, allowing for the use of a traditional SiO2 dielectric and damascene process, which means that no new material development is required and it eliminates damage for ultra narrow Cu line and ultra tiny interconnect structures. The tool features an automatic alignment structure, with no hard mask required. Finally, by selectively forming air gap interconnect structures in narrow line spaces, as opposed to wide line spaces, it provides both excellent thermal property for heat dissipation and excellent mechanical strength to resist pressure in packing.
“The benefits of Ultra iSFP are significant,” said David Wang, founder and CEO, ACM Research. “By capitalizing on the unique benefits of SFP, ULCMP and TFE in a single process tool, we have been able to successfully manufacture air gap interconnect structures with copper line-widths of less than 0.2 um while solving critical Cu/air-gap integration issues.”
The Ultra iSFP operates by passing the wafer through a low down force chemical mechanical planarization (CMP) process that uses endpoint detection to ensure a continuous 150nm Cu film, therefore protecting the underlying low-k structure. The wafer then undergoes a brush clean to remove large particles and a space alternating phase shift (SAPS) megasonic clean to remove tiny particles and oxide.
Following an in-tool, non-contact Cu thickness measurement, the wafer moves into the SFP process chamber to selectively remove the non-recess Cu to the barrier, followed by a bevel cleaning step. The clean wafer enters the TFE process where the barrier is removed after pre-heat, then the wafer is cooled before being transferred into the equipment front end module (EFEM) to be returned to the front opening unified pod (FOUP).
The electrochemical SFP polishing mechanism is a customer-proven critical enabling technology that ensures accurate polishing performance with no damage to the low-k and ultra low-k dielectrics. Based on a smart polishing control system, SFP is able to control global Cu line recess and dishing by using a pre-measured Cu film thickness map. Additionally, there is no erosion or deformation to the dielectric layer and barrier during the SFP polishing process, which can eliminate the damage of the Cu/low-k or ultra low-k dielectrics generated by the mechanical stress, effectively solving Cu/low-k and Cu/ultra low-k dielectric integration issues.
“The technology advances achieved with Ultra iSFP technology represent major breakthroughs in Cu/air-gap interconnect process integration. Due to its ability to reduce heat generation and increase heat dissipation, Ultra iSPF will become a critical technology to enable TSV applications,” added Wang.
It integrates the electrochemical mechanism of SFP with ultra low down force chemical mechanical planarization (ULCMP) and thermal flow etch (TFE) to take advantage of the specific benefits of each process step, while ensuring there is no damage to the underlying device structure.
Using the Ultra iSFP to form SiO2 based air gap interconnect structures offers several advantages. Its process is simple, allowing for the use of a traditional SiO2 dielectric and damascene process, which means that no new material development is required and it eliminates damage for ultra narrow Cu line and ultra tiny interconnect structures. The tool features an automatic alignment structure, with no hard mask required. Finally, by selectively forming air gap interconnect structures in narrow line spaces, as opposed to wide line spaces, it provides both excellent thermal property for heat dissipation and excellent mechanical strength to resist pressure in packing.
“The benefits of Ultra iSFP are significant,” said David Wang, founder and CEO, ACM Research. “By capitalizing on the unique benefits of SFP, ULCMP and TFE in a single process tool, we have been able to successfully manufacture air gap interconnect structures with copper line-widths of less than 0.2 um while solving critical Cu/air-gap integration issues.”
The Ultra iSFP operates by passing the wafer through a low down force chemical mechanical planarization (CMP) process that uses endpoint detection to ensure a continuous 150nm Cu film, therefore protecting the underlying low-k structure. The wafer then undergoes a brush clean to remove large particles and a space alternating phase shift (SAPS) megasonic clean to remove tiny particles and oxide.
Following an in-tool, non-contact Cu thickness measurement, the wafer moves into the SFP process chamber to selectively remove the non-recess Cu to the barrier, followed by a bevel cleaning step. The clean wafer enters the TFE process where the barrier is removed after pre-heat, then the wafer is cooled before being transferred into the equipment front end module (EFEM) to be returned to the front opening unified pod (FOUP).
The electrochemical SFP polishing mechanism is a customer-proven critical enabling technology that ensures accurate polishing performance with no damage to the low-k and ultra low-k dielectrics. Based on a smart polishing control system, SFP is able to control global Cu line recess and dishing by using a pre-measured Cu film thickness map. Additionally, there is no erosion or deformation to the dielectric layer and barrier during the SFP polishing process, which can eliminate the damage of the Cu/low-k or ultra low-k dielectrics generated by the mechanical stress, effectively solving Cu/low-k and Cu/ultra low-k dielectric integration issues.
“The technology advances achieved with Ultra iSFP technology represent major breakthroughs in Cu/air-gap interconnect process integration. Due to its ability to reduce heat generation and increase heat dissipation, Ultra iSPF will become a critical technology to enable TSV applications,” added Wang.
ACM Research Shanghai wins first order for Ultra C megasonic cleaning tool from leading Korean memory manufacturer
SHANGHAI, CHINA: ACM Research Shanghai Ltd has sold its first Ultra C 12-inch, single-wafer megasonic cleaning tool to a leading memory manufacturer based in Korea. Implementing ACM’s space alternated phase shift (SAPS) technology, the Ultra C delivers superior particle removal efficiency (PRE) with minimum material loss and uses extremely low chemical concentration functional water with no harsh chemicals. The tool will be implemented as part of the customer’s manufacturing process for its most advanced devices.
ACM’s Ultra C advanced SAPS technology shows an overwhelming improvement over alternative solutions, achieving an industry best PRE of 96 percent for particles 65 nm and above and 74 percent for particles between 44 nm and 65 nm, with material loss of less than 0.2 angstrom/cleaning step. By comparison, a competitive solution demonstrated a PRE of 84 percent for particles 65 nm and above and only 13 percent for particles between 44 nm and 65 nm in size according to customer data. With its superior PRE performance, the Ultra C offers customers a 1.3 percent increase in production yield at the 45nm node.
“This order clearly validates our cleaning technology,” said David Wang, founder and CEO of ACM Research. “Smaller device nodes have a very tight window for material loss, and the critical particle diameter is smaller, meaning that the small particles are more difficult to remove. Our SAPS megasonic technology has been proven and accepted by a leading IC manufacturer as a viable solution for removing these nano-scale particles. A clear breakthrough technology, the Ultra C is well positioned to displace current cleaning technologies at the 45 nm manufacturing node and beyond.”
The Ultra C targets advanced cleans in post-gate etch, pre-mask, post-implant, pre-oxidation, post-etch and pre-metal processes. The tool has shipped and final acceptance is expected shortly.
ACM’s proprietary space alternated phase shift (SAPS) megasonic technology enables highly uniform megasonic power density to achieve within wafer (WIW) and wafer-to-wafer (WTW) non-uniformity of less than 2 percent, compared to 10-20 percent non-uniformity offered by other single-wafer megasonic cleaning tools currently on the market.
Megasonic power is effective because the process causes cavitation (the formation of bubbles), which helps remove particles and bring them to the surface. The key is to control the mechanical process window of the megasonic energy so that there is enough energy to cause cavitation, but not so much that it causes damage to a patterned wafer.
As the process window for achieving a high PRE without causing damage is so narrow, it is critical to have excellent uniformity of energy distribution across the entire wafer. When megasonic power is not uniformly distributed, ‘hot spots’ form on the wafer where megasonic energy is higher, causing bubbles to collapse. ACM’s SAPS megasonic technology uses a stable cavitation bubble oscillation method, allowing the bubbles to continuously inflate and deflate without collapsing. SAPS technology enables damage-free megasonic cleaning with ultra-uniform energy distribution for optimal particle removal efficiencies.
ACM’s Ultra C advanced SAPS technology shows an overwhelming improvement over alternative solutions, achieving an industry best PRE of 96 percent for particles 65 nm and above and 74 percent for particles between 44 nm and 65 nm, with material loss of less than 0.2 angstrom/cleaning step. By comparison, a competitive solution demonstrated a PRE of 84 percent for particles 65 nm and above and only 13 percent for particles between 44 nm and 65 nm in size according to customer data. With its superior PRE performance, the Ultra C offers customers a 1.3 percent increase in production yield at the 45nm node.
“This order clearly validates our cleaning technology,” said David Wang, founder and CEO of ACM Research. “Smaller device nodes have a very tight window for material loss, and the critical particle diameter is smaller, meaning that the small particles are more difficult to remove. Our SAPS megasonic technology has been proven and accepted by a leading IC manufacturer as a viable solution for removing these nano-scale particles. A clear breakthrough technology, the Ultra C is well positioned to displace current cleaning technologies at the 45 nm manufacturing node and beyond.”
The Ultra C targets advanced cleans in post-gate etch, pre-mask, post-implant, pre-oxidation, post-etch and pre-metal processes. The tool has shipped and final acceptance is expected shortly.
ACM’s proprietary space alternated phase shift (SAPS) megasonic technology enables highly uniform megasonic power density to achieve within wafer (WIW) and wafer-to-wafer (WTW) non-uniformity of less than 2 percent, compared to 10-20 percent non-uniformity offered by other single-wafer megasonic cleaning tools currently on the market.
Megasonic power is effective because the process causes cavitation (the formation of bubbles), which helps remove particles and bring them to the surface. The key is to control the mechanical process window of the megasonic energy so that there is enough energy to cause cavitation, but not so much that it causes damage to a patterned wafer.
As the process window for achieving a high PRE without causing damage is so narrow, it is critical to have excellent uniformity of energy distribution across the entire wafer. When megasonic power is not uniformly distributed, ‘hot spots’ form on the wafer where megasonic energy is higher, causing bubbles to collapse. ACM’s SAPS megasonic technology uses a stable cavitation bubble oscillation method, allowing the bubbles to continuously inflate and deflate without collapsing. SAPS technology enables damage-free megasonic cleaning with ultra-uniform energy distribution for optimal particle removal efficiencies.
AppliedMicro showcases world's first 64-bit ARM v8 core
SANTA CLARA, USA: Applied Micro Circuits Corp. demonstrated core functionality of the world's first 64-bit ARM processor on an FPGA platform during ARM TechCon 2011. This milestone comes on the same day as ARM Holdings' announcement of its 64-bit ARMv8 instruction set architecture, and parallels AppliedMicro's launch of the industry's first 64-bit ARM "Server-on-a-Chip" solution in a single footprint, designed to deliver disruptively low power and cost points.
"The demonstration marks a fundamental achievement by AppliedMicro's engineering team to provide a proof of a single PMD core running both UBoot and 64-bit Linux," said Vinay Ravuri, Vice President of AppliedMicro's Embedded and Processing Business Unit. "It also provides pre-silicon customer evaluation of our 64-bit ARM solution and paves the way for a more sustainable future of cloud computing as we leverage this architecture to provide high-performance devices that consume less power and lower costs compared to today's server chips."
The demonstration platform consists of Xilinx Virtex-6 running Server SoC consisting of ARM-64 CPU complex, coherent CPU fabric, high performance I/O network, memory subsystem along with fully functional SoC subsystem.
Applied Micro's 64-bit processor family will leverage a large installed base of ARM software and hardware solutions and appeal to the open-source software community, similar to its 32-bit predecessor. With tremendous interest shown by top-tier OEMs and ODMs in the cloud computing space, the platform is fully enabled with server class open-source Linux distributions. Additionally Applied Micro is working with a number of server-class and embedded Linux vendors. Full open-source compilers and tool chains will be provided by AppliedMicro and ARM ecosystem partners.
Additionally, optimized compilers, tool chains, and debuggers will be provided by key strategic partners.
Full ecosystem support for the FPGA platform with performance metrics will be available for customer evaluation by the first half of 2012. A full suite of cloud computing applications driving various target workloads, such as Web, Memcached, Hadoop, Webserver, will also be available in that timeframe.
"The demonstration marks a fundamental achievement by AppliedMicro's engineering team to provide a proof of a single PMD core running both UBoot and 64-bit Linux," said Vinay Ravuri, Vice President of AppliedMicro's Embedded and Processing Business Unit. "It also provides pre-silicon customer evaluation of our 64-bit ARM solution and paves the way for a more sustainable future of cloud computing as we leverage this architecture to provide high-performance devices that consume less power and lower costs compared to today's server chips."
The demonstration platform consists of Xilinx Virtex-6 running Server SoC consisting of ARM-64 CPU complex, coherent CPU fabric, high performance I/O network, memory subsystem along with fully functional SoC subsystem.
Applied Micro's 64-bit processor family will leverage a large installed base of ARM software and hardware solutions and appeal to the open-source software community, similar to its 32-bit predecessor. With tremendous interest shown by top-tier OEMs and ODMs in the cloud computing space, the platform is fully enabled with server class open-source Linux distributions. Additionally Applied Micro is working with a number of server-class and embedded Linux vendors. Full open-source compilers and tool chains will be provided by AppliedMicro and ARM ecosystem partners.
Additionally, optimized compilers, tool chains, and debuggers will be provided by key strategic partners.
Full ecosystem support for the FPGA platform with performance metrics will be available for customer evaluation by the first half of 2012. A full suite of cloud computing applications driving various target workloads, such as Web, Memcached, Hadoop, Webserver, will also be available in that timeframe.
Tanner EDA and Dongbu HiTek release foundry-qualified PDK for BD180 low voltage 0.18um process
MONROVIA, USA & SEOUL, SOUTH KOREA: Tanner EDA, the catalyst for innovation for the design, layout and verification of analog and mixed-signal (A/MS) integrated circuits (ICs) and Dongbu HiTek, a world-class wafer fabricator, have finalized qualification of Dongbu HiTek’s 0.18um BD180LV process design kit (PDK).
The BD180LV kit integrates seamlessly into Tanner’s cohesive, integrated tool flow. Designers using Tanner EDA’s analog design suite, HiPer Silicon, will have certified libraries to draw on as they create ICs for production at Dongbu HiTek foundries, reducing design risk and providing faster time to market and higher quality of outcomes.
On May 3, 2011, Tanner EDA and Dongbu HiTek announced that they were jointly developing foundry-certified PDKs to deliver access to Dongbu HiTek’s analog foundry capabilities on Tanner EDA’s tool flow. This BCDMOS process is ideal for integrating analog circuits (using Bipolar), logic circuits (using CMOS) and high-voltage circuits (using DMOS) all on the same chip.
“Electronic designers no longer need to rely exclusively on analog IDMs for high-performance analog CMOS performance in order to differentiate products,” said Taek Soo Kim, VP of Dongbu’s HiTek’s technical engineering division. “As this collaboration with Tanner EDA shows, we continue to be committed to providing Dongbu customers with the best choices in electronic design automation software at critical development nodes.”
“We are pleased to add this qualified PDK to our portfolio,” said John Zuk, VP of marketing and strategy for Tanner EDA. “Our customers continue to cite the strong affinity of Tanner EDA tools in the power management space and continued collaboration with Dongbu HiTek enables us to deliver on our commitments of interoperability, productivity, and quicker design cycles for our customers.”
The BD180LV kit integrates seamlessly into Tanner’s cohesive, integrated tool flow. Designers using Tanner EDA’s analog design suite, HiPer Silicon, will have certified libraries to draw on as they create ICs for production at Dongbu HiTek foundries, reducing design risk and providing faster time to market and higher quality of outcomes.
On May 3, 2011, Tanner EDA and Dongbu HiTek announced that they were jointly developing foundry-certified PDKs to deliver access to Dongbu HiTek’s analog foundry capabilities on Tanner EDA’s tool flow. This BCDMOS process is ideal for integrating analog circuits (using Bipolar), logic circuits (using CMOS) and high-voltage circuits (using DMOS) all on the same chip.
“Electronic designers no longer need to rely exclusively on analog IDMs for high-performance analog CMOS performance in order to differentiate products,” said Taek Soo Kim, VP of Dongbu’s HiTek’s technical engineering division. “As this collaboration with Tanner EDA shows, we continue to be committed to providing Dongbu customers with the best choices in electronic design automation software at critical development nodes.”
“We are pleased to add this qualified PDK to our portfolio,” said John Zuk, VP of marketing and strategy for Tanner EDA. “Our customers continue to cite the strong affinity of Tanner EDA tools in the power management space and continued collaboration with Dongbu HiTek enables us to deliver on our commitments of interoperability, productivity, and quicker design cycles for our customers.”
GSA reports increased funding, M&A and IPO activity for Sept. 2011
USA: GSA has released September/Q3/9M Statistics from its Global Semiconductor Funding, IPO and M&A Update, including:
* In September 2011, 12 semiconductor companies raised $121.3 million, up 85.8 percent from the $65.3 million raised in August 2011.
* For the first nine months of 2011, 68 semiconductor deals raised $943.8 million, a dollar amount decrease of 7.1 percent YoY.
* In Q3 2011, 22 semiconductor companies raised $268.2 million, a dollar amount increase of 7.9 percent over Q2 2011 and 26.6 percent over Q3 2010.
* On September 13th, fabless semiconductor company Parade Technologies announced that public trading of its shares would begin as a result of the company’s initial public offering on Taiwan’s GreTai Securities Market.
* In September 2011, the number of semiconductor mergers and acquisitions (M&As) announced (i.e., M&As of entire fabless, IDM and semiconductor supplier companies, not sectors/product lines or foundry facilities) increased by eight MoM and decreased by one YoY.
* For the first nine months of 2011, 86 semiconductor M&A deals were announced, a 2.4 percent increase YoY.
* The third largest semiconductor M&A announced during the first nine months of 2011 took place in September when Broadcom Corp. purchased NetLogic Microsystems for $3.7 billion.
* In September 2011, 12 semiconductor companies raised $121.3 million, up 85.8 percent from the $65.3 million raised in August 2011.
* For the first nine months of 2011, 68 semiconductor deals raised $943.8 million, a dollar amount decrease of 7.1 percent YoY.
* In Q3 2011, 22 semiconductor companies raised $268.2 million, a dollar amount increase of 7.9 percent over Q2 2011 and 26.6 percent over Q3 2010.
* On September 13th, fabless semiconductor company Parade Technologies announced that public trading of its shares would begin as a result of the company’s initial public offering on Taiwan’s GreTai Securities Market.
* In September 2011, the number of semiconductor mergers and acquisitions (M&As) announced (i.e., M&As of entire fabless, IDM and semiconductor supplier companies, not sectors/product lines or foundry facilities) increased by eight MoM and decreased by one YoY.
* For the first nine months of 2011, 86 semiconductor M&A deals were announced, a 2.4 percent increase YoY.
* The third largest semiconductor M&A announced during the first nine months of 2011 took place in September when Broadcom Corp. purchased NetLogic Microsystems for $3.7 billion.
Free TI StarterWare enables quick and simple programming of TI embedded processors
DALLAS, USA: Embedded software programming comprises the majority of the product development cycle. Significantly reducing learning curves and accelerating development time in the embedded design process, Texas Instruments Inc. (TI) has announced its free StarterWare software packages, offering user-friendly, production-ready software for Sitara 32-bit ARM microprocessor (MPU), C6000 digital signal processor (DSP) and DSP + ARM developers.
StarterWare provides application developers with a flexible starting point that does not require the use of an operating system. In addition, StarterWare allows for easy migration to other TI embedded devices.
StarterWare simplifies and accelerates development
TI's new StarterWare software packages simplify the ARM MPU and DSP development process, offering application programming interfaces (APIs) to configure and interface with peripherals. In addition, StarterWare includes lightweight software stacks to enable USB, network and graphics functionality. Example code and application notes included with StarterWare reduce development time up to 10X.
The software packages do not require using or learning the intricacies of an operating system, enabling developers to accelerate time to market. Without having to access the hardware through an operating system, developers can fine-tune the system to achieve optimal resource management of the CPU, peripherals and memory, and to reduce system latencies by up to 500X compared to running under the Linux operating system. In more complex systems that may require an operating system to manage multiple data flows, StarterWare provides an optimum foundation. Many real-time operating system (RTOS) vendors are planning to leverage StarterWare in their offerings for TI embedded processors.
In addition to these benefits provided by StarterWare for TI's Sitara 32-bit ARM MPUs and C6000 DSPs, TI's DSP + ARM processors are supported with a simplified and low-latency inter-processor communication software layer that does not require an operating system, enabling processing and input/output (I/O) tasks to be efficiently shared between the two cores for optimized system performance.
StarterWare provides application developers with a flexible starting point that does not require the use of an operating system. In addition, StarterWare allows for easy migration to other TI embedded devices.
StarterWare simplifies and accelerates development
TI's new StarterWare software packages simplify the ARM MPU and DSP development process, offering application programming interfaces (APIs) to configure and interface with peripherals. In addition, StarterWare includes lightweight software stacks to enable USB, network and graphics functionality. Example code and application notes included with StarterWare reduce development time up to 10X.
The software packages do not require using or learning the intricacies of an operating system, enabling developers to accelerate time to market. Without having to access the hardware through an operating system, developers can fine-tune the system to achieve optimal resource management of the CPU, peripherals and memory, and to reduce system latencies by up to 500X compared to running under the Linux operating system. In more complex systems that may require an operating system to manage multiple data flows, StarterWare provides an optimum foundation. Many real-time operating system (RTOS) vendors are planning to leverage StarterWare in their offerings for TI embedded processors.
In addition to these benefits provided by StarterWare for TI's Sitara 32-bit ARM MPUs and C6000 DSPs, TI's DSP + ARM processors are supported with a simplified and low-latency inter-processor communication software layer that does not require an operating system, enabling processing and input/output (I/O) tasks to be efficiently shared between the two cores for optimized system performance.
IXYS Westcode intros 2.1kV high power distributed gate thyristor
BIEL, SWITZERLAND: IXYS Corp. announced that its wholly owned UK subsidiary, Westcode Ltd, launched the first in a new range of higher power higher efficiency distributed gate thyristors (DGT) with improved technology and thermal optimisation of silicon in the package. The first introduction is a 2.1kV/1.8kV device with an average current rating of 1700A.
“The new thyristor has a 56mm (2.21 inch) diameter silicon giving up to 20 percent increase in current rating, combined with faster switching when compared to our standard products, and includes a redesigned gate structure for improved dynamic performance,” commented Frank Wakeman, Marketing & Technical Support manager. “To allow compatibility with the minimum of adjustment to existing cooling/clamping system designs, the package of this new introduction fits within the same envelope as the current Westcode range of 50mm (1.97 inch) and 53mm (2.09 inch) silicon products. The new device is available with six turn-off (tq) options from 20usec to 60usec.”
He explained, “The increased silicon diameter and improved gate design allows for better optimisation of current rating and turn-off time thereby giving a faster device with higher current rating than Westcode’s established product range.”
The device is offered in two voltage classes and six tq limits. Part number R1700MC18# has Vdrm 1.8kV and R1700MC21# has Vdrm 2.1kV, both parts have Vrrm 1.8kV. Last character ‘#’ indicates the tq, E = 25usec, F = 30usec, G = 35usec, H = 40usec, J = 50usec and K = 60usec.
Typical applications for this device include induction heating power supplies for melting, billet heating and surface treatments, as well as resonant high power supplies, UPS, power pulse switches for lasers, Electric power for trains and motor control.
Further products are planned with voltage 1.2kV, 1.6kV, 2.5kV and 2.8kV and will be launched over the next 12 months. Each of these future introductions will offer the same performance advantages as the 2.1kV device.
“The new thyristor has a 56mm (2.21 inch) diameter silicon giving up to 20 percent increase in current rating, combined with faster switching when compared to our standard products, and includes a redesigned gate structure for improved dynamic performance,” commented Frank Wakeman, Marketing & Technical Support manager. “To allow compatibility with the minimum of adjustment to existing cooling/clamping system designs, the package of this new introduction fits within the same envelope as the current Westcode range of 50mm (1.97 inch) and 53mm (2.09 inch) silicon products. The new device is available with six turn-off (tq) options from 20usec to 60usec.”
He explained, “The increased silicon diameter and improved gate design allows for better optimisation of current rating and turn-off time thereby giving a faster device with higher current rating than Westcode’s established product range.”
The device is offered in two voltage classes and six tq limits. Part number R1700MC18# has Vdrm 1.8kV and R1700MC21# has Vdrm 2.1kV, both parts have Vrrm 1.8kV. Last character ‘#’ indicates the tq, E = 25usec, F = 30usec, G = 35usec, H = 40usec, J = 50usec and K = 60usec.
Typical applications for this device include induction heating power supplies for melting, billet heating and surface treatments, as well as resonant high power supplies, UPS, power pulse switches for lasers, Electric power for trains and motor control.
Further products are planned with voltage 1.2kV, 1.6kV, 2.5kV and 2.8kV and will be launched over the next 12 months. Each of these future introductions will offer the same performance advantages as the 2.1kV device.
IDT unveils world’s first ultra-low-power ±50 ppm CrystalFree CMOS oscillators
SAN JOSE, USA: Integrated Device Technology Inc. (IDT) announced that it has released the industry’s first CMOS oscillators to feature a breakthrough ±50 ppm frequency accuracy and ultra-low power consumption. The new devices replace traditional quartz crystal-based oscillators (XOs) for up to 75 percent power savings in any of a broad range of applications requiring a ±50 ppm timing reference, including computing, communications, and consumer markets.
IDT’s new 3LG family of CrystalFree CMOS oscillators guarantees ±50 ppm lifetime frequency accuracy. They are pin-to-pin compatible with existing quartz-based solutions, making the transition to a CMOS-based oscillator and the resulting power savings a seamless proposition. The devices support low-voltage-differential-signaling (LVDS), low-voltage positive emitter-coupled logic (LVPECL), and host-clock signal level (HCSL) standards for compatibility in a variety of applications.
IDT’s 3LG devices are designed using a standard silicon manufacturing process and are offered in industry-standard plastic packaging, resulting in lead time, reliability, and cost of ownership advantages over crystal oscillators. The 3LG family leverages the fundamental technology of the successful 3CN family of ±100 ppm products that are in volume production today.
“The transition away from quartz-based oscillators has begun. As the world-leader in silicon timing solutions, we continue to develop high-performance, low-power solutions to meet the needs of the market,” said Fred Zust, GM and VP, Communications Division at IDT. “Quartz-based oscillators have drawbacks in power, cost, availability, and reliability. IDT’s CrystalFree oscillators save up to 75 percent power versus their quartz-based counterparts, and also offer undeniable benefits for design simplicity, short lead times, and phenomenal reliability.”
“The semiconductor industry is moving forward at a rapid pace, but one thing that has remained unchanged for the last 50 years is the use of quartz crystal as the primary frequency source for electronics. To date, semiconductor-based frequency control products have not had the accuracy needed to challenge the incumbency of quartz in production systems,” said Sergis Mushell, principal research analyst at Gartner. “With superior pricing and performance versus crystal-based solutions, these semiconductor-based frequency sources will have a significant impact on the crystal oscillator market.”
The new devices generate stable frequencies up to 125 MHz and offer high-performance phase jitter of less than 1 picosecond over the wide frequency offset of 12 kHz to 20 MHz. In addition, semiconductor-grade shock and vibration resistance provides extreme reliability over the lifetime of the device, while the ultra-small, low-profile packages conserve valuable board area in compact designs.
The IDT 3LG CrystalFree ±50 ppm oscillators are currently sampling to qualified customers. The IDT 3CN CrystalFree ±100 ppm oscillators are in full production today, available in industry-standard packages. For high volume applications, IDT’s CrystalFree oscillators can support fast, high-volume production with short lead times, typically fewer than four weeks, to support any frequency requirement.
IDT’s new 3LG family of CrystalFree CMOS oscillators guarantees ±50 ppm lifetime frequency accuracy. They are pin-to-pin compatible with existing quartz-based solutions, making the transition to a CMOS-based oscillator and the resulting power savings a seamless proposition. The devices support low-voltage-differential-signaling (LVDS), low-voltage positive emitter-coupled logic (LVPECL), and host-clock signal level (HCSL) standards for compatibility in a variety of applications.
IDT’s 3LG devices are designed using a standard silicon manufacturing process and are offered in industry-standard plastic packaging, resulting in lead time, reliability, and cost of ownership advantages over crystal oscillators. The 3LG family leverages the fundamental technology of the successful 3CN family of ±100 ppm products that are in volume production today.
“The transition away from quartz-based oscillators has begun. As the world-leader in silicon timing solutions, we continue to develop high-performance, low-power solutions to meet the needs of the market,” said Fred Zust, GM and VP, Communications Division at IDT. “Quartz-based oscillators have drawbacks in power, cost, availability, and reliability. IDT’s CrystalFree oscillators save up to 75 percent power versus their quartz-based counterparts, and also offer undeniable benefits for design simplicity, short lead times, and phenomenal reliability.”
“The semiconductor industry is moving forward at a rapid pace, but one thing that has remained unchanged for the last 50 years is the use of quartz crystal as the primary frequency source for electronics. To date, semiconductor-based frequency control products have not had the accuracy needed to challenge the incumbency of quartz in production systems,” said Sergis Mushell, principal research analyst at Gartner. “With superior pricing and performance versus crystal-based solutions, these semiconductor-based frequency sources will have a significant impact on the crystal oscillator market.”
The new devices generate stable frequencies up to 125 MHz and offer high-performance phase jitter of less than 1 picosecond over the wide frequency offset of 12 kHz to 20 MHz. In addition, semiconductor-grade shock and vibration resistance provides extreme reliability over the lifetime of the device, while the ultra-small, low-profile packages conserve valuable board area in compact designs.
The IDT 3LG CrystalFree ±50 ppm oscillators are currently sampling to qualified customers. The IDT 3CN CrystalFree ±100 ppm oscillators are in full production today, available in industry-standard packages. For high volume applications, IDT’s CrystalFree oscillators can support fast, high-volume production with short lead times, typically fewer than four weeks, to support any frequency requirement.
LSI announces agreement to acquire SandForce
MILPITAS, USA: LSI Corp. announced that it has signed a definitive agreement to acquire SandForce Inc., the leading provider of flash storage processors for enterprise and client flash solutions and solid state drives (SSDs). Under the agreement, LSI will pay approximately $322 million in cash, net of cash assumed, and assume approximately $48 million of unvested stock options and restricted shares held by SandForce employees.
SandForce’s award-winning products include flash storage processors at the heart of PCIe flash adapters and SSDs. Flash storage processors provide the intelligence required to deliver the performance and low-latency benefits of flash storage in enterprise and client applications. With market-proven, differentiated DuraClass technology, SandForce flash storage processors improve the reliability, endurance and power efficiency of flash-based storage solutions.
The acquisition greatly enhances LSI's competitive position in the fast-growing server and storage PCIe flash adapter market, where the WarpDrive family of products from LSI already uses SandForce flash storage processors. The complementary combination of LSI’s custom capability and SandForce’s standard product offering propels LSI into an industry-leading position in the rapidly growing, high-volume flash storage processor market space for ultrabook, notebook and enterprise SSD and flash solutions.
“Flash-based solutions are critical for accelerating application performance in servers, storage and client devices,” said Abhi Talwalkar, LSI president and CEO. “Adding SandForce’s technology to LSI’s broad storage portfolio is consistent with our mission to accelerate storage and networking. The acquisition represents a significant, rapidly growing market opportunity for LSI over the next several years.”
Michael Raam, SandForce president and CEO, said: “The combination of SandForce and LSI allows us to deliver differentiated solutions in the PCIe flash adapter segment by tightly integrating flash memory and management. In addition, leveraging our flash storage processors with LSI’s comprehensive IP portfolio and leading-edge silicon design platforms will lead to innovative solutions.”
The transaction is expected to close early in the first quarter of 2012 subject to customary closing conditions and regulatory approvals. Upon closing, the SandForce team will become part of LSI’s newly formed Flash Components Division, with Raam as general manager.
SandForce’s award-winning products include flash storage processors at the heart of PCIe flash adapters and SSDs. Flash storage processors provide the intelligence required to deliver the performance and low-latency benefits of flash storage in enterprise and client applications. With market-proven, differentiated DuraClass technology, SandForce flash storage processors improve the reliability, endurance and power efficiency of flash-based storage solutions.
The acquisition greatly enhances LSI's competitive position in the fast-growing server and storage PCIe flash adapter market, where the WarpDrive family of products from LSI already uses SandForce flash storage processors. The complementary combination of LSI’s custom capability and SandForce’s standard product offering propels LSI into an industry-leading position in the rapidly growing, high-volume flash storage processor market space for ultrabook, notebook and enterprise SSD and flash solutions.
“Flash-based solutions are critical for accelerating application performance in servers, storage and client devices,” said Abhi Talwalkar, LSI president and CEO. “Adding SandForce’s technology to LSI’s broad storage portfolio is consistent with our mission to accelerate storage and networking. The acquisition represents a significant, rapidly growing market opportunity for LSI over the next several years.”
Michael Raam, SandForce president and CEO, said: “The combination of SandForce and LSI allows us to deliver differentiated solutions in the PCIe flash adapter segment by tightly integrating flash memory and management. In addition, leveraging our flash storage processors with LSI’s comprehensive IP portfolio and leading-edge silicon design platforms will lead to innovative solutions.”
The transaction is expected to close early in the first quarter of 2012 subject to customary closing conditions and regulatory approvals. Upon closing, the SandForce team will become part of LSI’s newly formed Flash Components Division, with Raam as general manager.
GigOptix TFPS Mach-Zehnder modulators now fully Telcordia qualified
SAN JOSE, USA: GigOptix Inc., a leading fabless supplier of semiconductor and optical components that enable high-speed information streaming, today announced the completion of reliability qualification for its Mach-Zehnder Modulators (MZM) that are implemented using GigOptix’s proprietary Thin Film Polymer on Silicon (TFPS) technology.
The full compliance of the TFPS modulator series of products as tested against Telcordia GR-468 standard, is a monumental milestone for GigOptix, as this is the first polymer modulator to come to market, fully qualified, that will truly disrupt the current market for Mach-Zehnder Modulators (MZM).
The TFPS modulators offer significant advantages over the existing crystalline semiconductor technologies used today. GigOptix’s proprietary material enables industry leading low drive voltage in the smallest form factor available. The low drive voltage reduces power consumption by more than 20 percent compared to competing modulator technologies, while the small form factor enables smaller 300pin optical transponders. The modulators also offer simpler manufacturing processes and larger bandwidth.
Intrinsic polymer material properties and TFPS modulator processing allows the modulator to reside on the same silicon chip as the silicon-based drivers, offering an integration platform for small footprint components. The technology also allows for the integration of the modulator, laser, and driver in a small footprint module.
Dr. Raluca Dinu, GigOptix’s VP and GM of Optics, states, “After more than 10 years of hard work and groundbreaking innovation, our revolutionary TFPS products and materials are now fully qualified and available commercially to the market.”
“Three years ago, when GigOptix acquired Lumera, we could only dream of what the proprietary polymer material could accomplish and with the full Telcordia qualification of the TFPS modulators, we finally see one of those dreams turn to reality,” stated Dr. Avi Katz, chairman and CEO of GigOptix. “The team has brought a highly innovative product from a R&D experiment into a fully qualified, highly disruptive, commercial product. I have the deepest of respect and gratitude for the entire GigOptix team in bringing this vision to fruition.”
Passing the stringent requirements of the Telcordia GR-468 is essential, as it demonstrates that the TFPS modulators meet the long-term reliability standards required by today’s telecommunication sub-system and system integrators.
The TFPS modulators have passed the specific testing requirements as outline in the Telcordia GR-468 standard including:
High Temperature Operation Lifetime (HTOL) tested at 85° C
Temperature cycling
Low temperature storage
Vibration, mechanical and thermal shock
Fiber pull, twist, and cable retention testing.
The LX8401 (40G DPSK) MZM is available in production quantities. The LX8220 (40G DQPSK), LX8900 (100G Dual Drive NRZ), and LX8901 (100G DPSK) MZMs are available for sampling.
The full compliance of the TFPS modulator series of products as tested against Telcordia GR-468 standard, is a monumental milestone for GigOptix, as this is the first polymer modulator to come to market, fully qualified, that will truly disrupt the current market for Mach-Zehnder Modulators (MZM).
The TFPS modulators offer significant advantages over the existing crystalline semiconductor technologies used today. GigOptix’s proprietary material enables industry leading low drive voltage in the smallest form factor available. The low drive voltage reduces power consumption by more than 20 percent compared to competing modulator technologies, while the small form factor enables smaller 300pin optical transponders. The modulators also offer simpler manufacturing processes and larger bandwidth.
Intrinsic polymer material properties and TFPS modulator processing allows the modulator to reside on the same silicon chip as the silicon-based drivers, offering an integration platform for small footprint components. The technology also allows for the integration of the modulator, laser, and driver in a small footprint module.
Dr. Raluca Dinu, GigOptix’s VP and GM of Optics, states, “After more than 10 years of hard work and groundbreaking innovation, our revolutionary TFPS products and materials are now fully qualified and available commercially to the market.”
“Three years ago, when GigOptix acquired Lumera, we could only dream of what the proprietary polymer material could accomplish and with the full Telcordia qualification of the TFPS modulators, we finally see one of those dreams turn to reality,” stated Dr. Avi Katz, chairman and CEO of GigOptix. “The team has brought a highly innovative product from a R&D experiment into a fully qualified, highly disruptive, commercial product. I have the deepest of respect and gratitude for the entire GigOptix team in bringing this vision to fruition.”
Passing the stringent requirements of the Telcordia GR-468 is essential, as it demonstrates that the TFPS modulators meet the long-term reliability standards required by today’s telecommunication sub-system and system integrators.
The TFPS modulators have passed the specific testing requirements as outline in the Telcordia GR-468 standard including:
High Temperature Operation Lifetime (HTOL) tested at 85° C
Temperature cycling
Low temperature storage
Vibration, mechanical and thermal shock
Fiber pull, twist, and cable retention testing.
The LX8401 (40G DPSK) MZM is available in production quantities. The LX8220 (40G DQPSK), LX8900 (100G Dual Drive NRZ), and LX8901 (100G DPSK) MZMs are available for sampling.
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