TAIPEI, TAIWAN: CSR announced the SiRFatlasV multifunction GPS system processor, a next-generation system-on-chip device with higher levels of integration, performance and cost-effectiveness that enables manufacturers to create high-volume, value-priced consumer navigation and location-aware products.
Available now in production quantities, SiRFatlasV’s ARM 11 and DSP dual-core architecture delivers high performance GPS, high-MIPs application computing and robust multifunction capabilities on a single chip to reduce system cost and size while speeding time to market.
“SiRFatlasV is the next step in the evolution of our mainstream navigation platform, bringing even greater functionality on chip and delivering faster fixes and higher performance than ever before while reducing overall power consumption, system cost and size,” said Kanwar Chadha, chief marketing officer at CSR.
“All of this plus the considerable time-to-market advantages of our Synergy connectivity solution make SiRFatlasV the platform of choice for a new generation of mainstream PND and location-aware consumer devices.”
The SiRFatlasV processor combines on a single chip a 500- or 664-MHz ARM11 processor core with vector floating point unit; advanced, autonomous GPS/Galileo baseband DSP core with available SiRFAlwaysFix technology, DDR2, Mobile DDR, SD/MMC/MMC+ and NAND flash memory controllers; audio DAC; LCD touch panel controller, video post processing accelerator; USB 2.0 and other connectivity interfaces and a complete power management unit.
This high degree of integration reduces parts count and bill of material (BOM) costs, power requirements and PC board size while simplifying design and speeding development and time to market.
“Microsoft is excited to be working with CSR to deliver rich, specialized application experiences on the SiRFatlasV navigation platform,” said Kim Chau, senior partner manager for Windows Embedded at Microsoft Corp. “With SiRFatlasV, CSR has created an optimized and developer-friendly Windows Embedded CE 6.0 platform for mobile navigation, and we look forward to working with CSR to continue to drive innovation and differentiation in this market.”
Windows Embedded CE 6.0 is a componentized, real-time operating system that delivers compelling experiences on a wide range of small footprint consumer and enterprise devices. By building on the high performance and highly reliable Windows Embedded CE platform, device makers can bring their device to market quickly and efficiently.
“We are very pleased with the customer and partner response to SiRFatlasV,” said Ahmet Alpdemir, senior vice president for the Automotive/PND business unit of CSR. “AtlasV is already in use by a number of leading original equipment and original device manufacturers, including GlobalSat Technology Corporation, Mango Research Corp., Mobile Devices, Topicon HK Limited and YF International Limited.”
Using CSR Synergy, the SiRFatlasV processor can be seamlessly integrated with CSR’s audio and connectivity platforms incorporating a broad range of technologies – Bluetooth, Bluetooth low energy, Wi-Fi, echo cancellation, noise suppression, FM receive and transmit and more.
CSR Synergy ensures that all of these systems work together as a unified platform, enabling technologies such as Bluetooth and Wi-Fi to coexist in the same system environment without interfering with one another or degrading performance. This simplifies design engineering and helps achieve an overall improvement in the end-user experience.
Thursday, May 27, 2010
Northrop Grumman doubles frequency of fastest reported IC
REDONDO BEACH, USA: Northrop Grumman Corporation (NYSE:NOC) has set a new electronics performance record with a Terahertz Monolithic Integrated Circuit (TMIC) operating at 0.67 terahertz (THz), or 0.67 trillion cycles per second.
Developed at the company's Simon Ramo Microelectronics Center under a contract with the Defense Advanced Research Projects Agency's (DARPA) Terahertz Electronics program, this new performance record more than doubles the frequency of the fastest reported integrated circuit.
Dr. William Deal, THz Electronics program manager for Northrop Grumman's Aerospace Systems sector, detailed the performance of this new TMIC amplifier today at the Institute of Electrical and Electronics Engineers' (IEEE) International Microwave Symposium being held in Anaheim, Calif. He told fellow scientists that the TMIC amplifier is the first of its kind operating at 670 GHz.
He said: "A variety of applications exist at these frequencies. These devices could double the bandwidth, or information carrying capacity, for future military communications networks. TMIC amplifiers will enable more sensitive radar and produce sensors with highly improved resolution."
The goal of DARPA's Terahertz Electronics program is to develop the critical device and integration technologies necessary to realize compact, high-performance, electronic circuits that operate at center frequencies exceeding 1.0 THz. Managed by DARPA's Microsystems Technology Office, the program focuses on two areas – terahertz high-power amplifier modules, and terahertz transistor electronics.
According to Dr. John Albrecht, THz Electronics program manager for DARPA, "The success of the THz Electronics program will lead to revolutionary applications such as THz imaging systems, sub-mm-wave ultra-wideband ultra-high-capacity communication links, and sub-mm-wave single-chip widely-tunable synthesizers for explosive detection spectroscopy."
A transistor amplifier magnifies input signals to yield a significantly larger output signal. In 2007, Northrop Grumman set a new world record for transistor speed with an ultra-fast device to provide much higher frequency and bandwidth capabilities for future military communications, radar and intelligence applications.
The company produced and demonstrated an indium phosphide-based High Electron Mobility Transistor (InP HEMT) with a maximum frequency of operation of more than 1,000 gigahertz, or greater than one terahertz.
Developed at the company's Simon Ramo Microelectronics Center under a contract with the Defense Advanced Research Projects Agency's (DARPA) Terahertz Electronics program, this new performance record more than doubles the frequency of the fastest reported integrated circuit.
Dr. William Deal, THz Electronics program manager for Northrop Grumman's Aerospace Systems sector, detailed the performance of this new TMIC amplifier today at the Institute of Electrical and Electronics Engineers' (IEEE) International Microwave Symposium being held in Anaheim, Calif. He told fellow scientists that the TMIC amplifier is the first of its kind operating at 670 GHz.
He said: "A variety of applications exist at these frequencies. These devices could double the bandwidth, or information carrying capacity, for future military communications networks. TMIC amplifiers will enable more sensitive radar and produce sensors with highly improved resolution."
The goal of DARPA's Terahertz Electronics program is to develop the critical device and integration technologies necessary to realize compact, high-performance, electronic circuits that operate at center frequencies exceeding 1.0 THz. Managed by DARPA's Microsystems Technology Office, the program focuses on two areas – terahertz high-power amplifier modules, and terahertz transistor electronics.
According to Dr. John Albrecht, THz Electronics program manager for DARPA, "The success of the THz Electronics program will lead to revolutionary applications such as THz imaging systems, sub-mm-wave ultra-wideband ultra-high-capacity communication links, and sub-mm-wave single-chip widely-tunable synthesizers for explosive detection spectroscopy."
A transistor amplifier magnifies input signals to yield a significantly larger output signal. In 2007, Northrop Grumman set a new world record for transistor speed with an ultra-fast device to provide much higher frequency and bandwidth capabilities for future military communications, radar and intelligence applications.
The company produced and demonstrated an indium phosphide-based High Electron Mobility Transistor (InP HEMT) with a maximum frequency of operation of more than 1,000 gigahertz, or greater than one terahertz.
Cypress and BITS Pilani - K.K. Birla Goa Campus team up on new PSoC 3 lab
BANGALORE, INDIA: Cypress Semiconductor Corp. and the Birla Institute of Technology and Science (BITS), Pilani - K.K. Birla Goa Campus (BPKKBGC) signed a memorandum of understanding for collaborative research and funded lab development based on the PSoC 3 programmable system-on-chip. The MoU was signed by Prof. K.E. Raman, Director, BPKKBGC and Patrick Kane, Director of Cypress University Alliance.
Patrick Kane visited the campus where he inaugurated a state-of-the-art PSoC 3 lab—the first of its kind in India. The lab will expose students to the PSoC platform, a flexible family of devices with programmable analog and digital blocks integrated with a microcontroller. With its unique architecture, PSoC provides an unrivaled learning platform for embedded design students and will enable them to create projects and solutions for embedded systems.
“Our focus is to excite students about new technologies and hence grow the pool of budding, talented engineers from India. The PSoC lab will allow students to innovate and work on high-tech projects,” said Patrick Kane. He and his team interacted extensively with both students and faculty at BPKKBGC. They also conducted a workshop for the Electrical, Electronics and Instrumentation Group.
“The lab has added an extra dimension to the student learning experience and has resulted in a unique learning platform where students now receive real-world, hands-on experience in developing applications,” said Prof. Raman.
Students from BPKKBGC have implemented a number of projects using PSoC 1 technology. Some of these include a BLDC motor driver, a pH meter, an accelerometer based tilt sensor, a PWM driven hexapod etc. These projects are currently being developed using the new PSoC 3 platform, which uses an 8051 core as well a programmable analog and digital modules.
Students have also been involved in research based projects such as study of battery charging algorithms using the PSoC. They have also assisted Cypress in development of the Power Line Communication solution. A PSoC 3 manual by BITS Goa is also in the pipeline.
Patrick Kane visited the campus where he inaugurated a state-of-the-art PSoC 3 lab—the first of its kind in India. The lab will expose students to the PSoC platform, a flexible family of devices with programmable analog and digital blocks integrated with a microcontroller. With its unique architecture, PSoC provides an unrivaled learning platform for embedded design students and will enable them to create projects and solutions for embedded systems.
“Our focus is to excite students about new technologies and hence grow the pool of budding, talented engineers from India. The PSoC lab will allow students to innovate and work on high-tech projects,” said Patrick Kane. He and his team interacted extensively with both students and faculty at BPKKBGC. They also conducted a workshop for the Electrical, Electronics and Instrumentation Group.
“The lab has added an extra dimension to the student learning experience and has resulted in a unique learning platform where students now receive real-world, hands-on experience in developing applications,” said Prof. Raman.
Students from BPKKBGC have implemented a number of projects using PSoC 1 technology. Some of these include a BLDC motor driver, a pH meter, an accelerometer based tilt sensor, a PWM driven hexapod etc. These projects are currently being developed using the new PSoC 3 platform, which uses an 8051 core as well a programmable analog and digital modules.
Students have also been involved in research based projects such as study of battery charging algorithms using the PSoC. They have also assisted Cypress in development of the Power Line Communication solution. A PSoC 3 manual by BITS Goa is also in the pipeline.
Mercury Computer Systems enables scalable, cost-effective solutions with MicroTCA platform
CHELMSFORD, USA: Mercury Computer Systems Inc., a leading provider of open, embedded, high-performance computing systems, software, and services for image, sensor, and signal processing applications, announced a systems-level enhancement for solutions based on the MicroTCA standard.
The new, innovative six-slot chassis is part of Mercury’s Ensemble 2000 MicroTCA Platform, a standards-based solution built around the power, functionality, and scalability of RapidIO, Ethernet, IPMI, AdvancedMC, and MicroTCA industry standards.
Switches are built into the chassis backplane to support both Gigabit Ethernet (base interface) and a choice of communications fabrics including RapidIO, 10 Gigabit Ethernet, and PCI Express. The backplane also includes built-in system manager functionality. This built-in functionality means that a separate MCH module is not required, reducing costs and allowing all slots to be configured with AMCs.
“Designers of sophisticated industrial equipment, in industries such as Communications and Semiconductor Manufacturing, need high-performance, high-bandwidth embedded computing in cost-effective packages,” said Steve McPherson, Director of Business Development at Mercury. “With its compact size, scalability, and integrated system functionality, our new six-slot MicroTCA chassis provides a flexible platform for building those types of solutions.”
The new Ensemble 2000 chassis is also appropriate for a wide range of system sizes, with multi-chassis scalability built into the design. It supports mechanical stacking in a 19-inch rack; and the base interface, fabric interface, and clock can all be daisy-chained across multiple chassis.
Robust system configurations are also supported by Mercury’s industry-leading family of processor AMCs, including Xilinx FPGAs, TI DSPs, PowerQUICC, Power Architecture MPC 8641D, and Intel Penryn processors.
The new, innovative six-slot chassis is part of Mercury’s Ensemble 2000 MicroTCA Platform, a standards-based solution built around the power, functionality, and scalability of RapidIO, Ethernet, IPMI, AdvancedMC, and MicroTCA industry standards.
Switches are built into the chassis backplane to support both Gigabit Ethernet (base interface) and a choice of communications fabrics including RapidIO, 10 Gigabit Ethernet, and PCI Express. The backplane also includes built-in system manager functionality. This built-in functionality means that a separate MCH module is not required, reducing costs and allowing all slots to be configured with AMCs.
“Designers of sophisticated industrial equipment, in industries such as Communications and Semiconductor Manufacturing, need high-performance, high-bandwidth embedded computing in cost-effective packages,” said Steve McPherson, Director of Business Development at Mercury. “With its compact size, scalability, and integrated system functionality, our new six-slot MicroTCA chassis provides a flexible platform for building those types of solutions.”
The new Ensemble 2000 chassis is also appropriate for a wide range of system sizes, with multi-chassis scalability built into the design. It supports mechanical stacking in a 19-inch rack; and the base interface, fabric interface, and clock can all be daisy-chained across multiple chassis.
Robust system configurations are also supported by Mercury’s industry-leading family of processor AMCs, including Xilinx FPGAs, TI DSPs, PowerQUICC, Power Architecture MPC 8641D, and Intel Penryn processors.
Docea announces power and thermal modeling and analysis capabilities for Aceplorer, previews AcePowerModeler
MOIRANS-GRENOBLE, FRANCE: Docea Power, the design-for-low-power company that delivers software solutions for power and thermal analysis at the architectural level, today announced a new version of its system-level power and thermal modeling platform: Aceplorer 2.0.
The new version adds project management capabilities to boost productivity and a link to virtual platforms to assess the impact of complex scenarios and embedded software on a system’s power consumption.
At the 47th Design Automation Conference (DAC) next month, Docea will preview AcePowerModeler, a power model generator tool that closes the loop between implementation and architectural modeling by automating the creation of power models from lower level simulation and characterization data.
Two main challenges face system architects for power simulation at a high abstraction level:
* How to describe the activity and capture a realistic scenario for the architecture, and
* Where to get power models to describe the architecture.
Aceplorer 2.0 answers the first challenge by linking to virtual platforms to allow the import of traces describing the activity in standard VCD (Value Change Dump) format. With new platforms and systems-on-chip embedding more and more functions and software, the complexity of use cases and use scenarios is exploding.
With this link, architects can continue to optimize the performance of their designs on their current flow, and have the possibility to measure the impact of complex scenarios and embedded software on the power consumption of their design’s architecture. Since the VCD output format is a standard, Aceplorer can now be used in combination with any performance analysis flow.
As for the second challenge, Ghislain Kaiser, CEO, Docea Power, noted: “In most design projects, around 80 percent of the blocks are reused with some variation from previous designs. Within these legacy designs, there is a tremendous amount of data from power simulations at the gate level or from netlists and from measurements. It can take hours of simulations and testbench setups to extract this data, and now with Aceplorer 2.0 it can be exploited by system architects.”
AcePowerModeler automates the generation of power models from power figures and tables extracted from low level descriptions and from measurements. These models can be re-used by architects at a higher abstraction level for much faster simulations allowing architectural exploration and optimization with no loss of accuracy.
Aceplorer 2.0 is available now. AcePowerModeler is available now for select customers, and will be released in Q4. It can be used with Aceplorer or stand alone.
The new version adds project management capabilities to boost productivity and a link to virtual platforms to assess the impact of complex scenarios and embedded software on a system’s power consumption.
At the 47th Design Automation Conference (DAC) next month, Docea will preview AcePowerModeler, a power model generator tool that closes the loop between implementation and architectural modeling by automating the creation of power models from lower level simulation and characterization data.
Two main challenges face system architects for power simulation at a high abstraction level:
* How to describe the activity and capture a realistic scenario for the architecture, and
* Where to get power models to describe the architecture.
Aceplorer 2.0 answers the first challenge by linking to virtual platforms to allow the import of traces describing the activity in standard VCD (Value Change Dump) format. With new platforms and systems-on-chip embedding more and more functions and software, the complexity of use cases and use scenarios is exploding.
With this link, architects can continue to optimize the performance of their designs on their current flow, and have the possibility to measure the impact of complex scenarios and embedded software on the power consumption of their design’s architecture. Since the VCD output format is a standard, Aceplorer can now be used in combination with any performance analysis flow.
As for the second challenge, Ghislain Kaiser, CEO, Docea Power, noted: “In most design projects, around 80 percent of the blocks are reused with some variation from previous designs. Within these legacy designs, there is a tremendous amount of data from power simulations at the gate level or from netlists and from measurements. It can take hours of simulations and testbench setups to extract this data, and now with Aceplorer 2.0 it can be exploited by system architects.”
AcePowerModeler automates the generation of power models from power figures and tables extracted from low level descriptions and from measurements. These models can be re-used by architects at a higher abstraction level for much faster simulations allowing architectural exploration and optimization with no loss of accuracy.
Aceplorer 2.0 is available now. AcePowerModeler is available now for select customers, and will be released in Q4. It can be used with Aceplorer or stand alone.
UMC uses Silicon Frontline’s Field Solver to generate reference extraction data
LOS GATOS, USA: Silicon Frontline Technology Inc. (SFT) announced that its 3D extraction software for post-layout verification F3D (Fast 3D) has been qualified by United Microelectronics Corp. (UMC), a leading global semiconductor foundry, as the reference field solver for parasitic extraction.
UMC verified F3D’s accuracy through extensive comparison with internal benchmarks. The reliability and repeatability of results led to UMC’s adoption of F3D to generate reference data. Silicon Frontline’s F3D provides field solver accuracy for full-chip design, enabling higher quality extraction and faster post-layout verification closure.
“We are excited to add F3D as another reference field solver at UMC. We adopted Silicon Frontline’s F3D as a 3D extractor because it provides accuracy for many styles of circuitry, including high precision analog such as ADCs,” said Stephen Fu, Director of IP Development and Design Support at UMC. “This opens the door to providing higher quality silicon to customers.”
“Having UMC, a leading and well-respected silicon foundry, select F3D for generating reference parasitic extraction data boosts customers’ confidence in our results,” added Yuri Feinberg, Silicon Frontline CEO. “As customers experience F3D’s ability to accurately match sensitive parasitics, they realize more aggressive design goals are achievable and accurate design verification is possible.”
Silicon Frontline’s post-layout verification software guarantees accuracy and high performance by using rigorous 3D technology to extract parasitics. Users have the option to specify the level of accuracy desired, net by net, at the block level or with regular expressions. By guaranteeing accuracy, Silicon Frontline is ensuring the resulting parasitics are correct within the user-specified accuracy.
In July 2009, UMC validated F3D for its nanometer design processes.
UMC verified F3D’s accuracy through extensive comparison with internal benchmarks. The reliability and repeatability of results led to UMC’s adoption of F3D to generate reference data. Silicon Frontline’s F3D provides field solver accuracy for full-chip design, enabling higher quality extraction and faster post-layout verification closure.
“We are excited to add F3D as another reference field solver at UMC. We adopted Silicon Frontline’s F3D as a 3D extractor because it provides accuracy for many styles of circuitry, including high precision analog such as ADCs,” said Stephen Fu, Director of IP Development and Design Support at UMC. “This opens the door to providing higher quality silicon to customers.”
“Having UMC, a leading and well-respected silicon foundry, select F3D for generating reference parasitic extraction data boosts customers’ confidence in our results,” added Yuri Feinberg, Silicon Frontline CEO. “As customers experience F3D’s ability to accurately match sensitive parasitics, they realize more aggressive design goals are achievable and accurate design verification is possible.”
Silicon Frontline’s post-layout verification software guarantees accuracy and high performance by using rigorous 3D technology to extract parasitics. Users have the option to specify the level of accuracy desired, net by net, at the block level or with regular expressions. By guaranteeing accuracy, Silicon Frontline is ensuring the resulting parasitics are correct within the user-specified accuracy.
In July 2009, UMC validated F3D for its nanometer design processes.
Graphene Laboratories, CVD Equipment in exclusive distribution agreement for CVD Graphene products
RONKONKOMA, USA: CVD Equipment Corp. has signed an exclusive distribution agreement with Graphene Laboratories Inc. for Chemical Vapor Deposited (CVD) Graphene products.
Under this Agreement CVD Equipment Corporation will manufacture CVD grown Graphene based materials and products and Graphene Laboratories, Inc. will market and sell them on a worldwide basis.
CVD Equipment’s Application Laboratory provides process development and material growth services for a wide range of advanced nanomaterials, i.e., Carbon Nanotubes, Silicon and other Nanowires, CVD Graphene, Transparent Conducting Oxide (TCO) materials and other CVD processes. It hosts a range of CVD research and production equipment that will be utilized for CVD Graphene production.
Graphene is a novel nanomaterial carbon film that is only a few atoms thick and possesses unparalleled electrical and mechanical properties as well as supreme stability and durability.
CVD grown Graphene is projected to be used for production of Graphene-based electronics, sensors, MEMS, solar batteries, etc. Some of the CVD Graphene products sold by Graphene Laboratories Inc. will be marked with one or more trademarks from CVD Equipment, such as nMEMStarter, nFoil, and CVDGraphene.
“The ability to mass produce CVD Graphene is a key milestone for Graphene commercialization,” said Dr. Elena Polyakova, CEO of Graphene Laboratories.
“Currently, the progress in development of Graphene-based commercial products is largely stalled by a lack of supply of high-quality wafer-size Graphene films. CVD grown Graphene is well positioned to address this market demand. We anticipate strong interest from academic and industrial customers in our CVD Graphene products and this is an extremely important partnership for our Company. By selecting CVD Equipment Corporation as our partner, we will be able to expand our Graphene based product offerings and greatly advance the development of various Graphene enabled products.”
"CVD Equipment is focusing on enabling the commercialization of tomorrow’s technologies,” says Karlheinz Strobl, VP of Business Development of CVD Equipment.
“By leveraging the process development and manufacturing capabilities of our Application Laboratory and by collaborating with Graphene Laboratories Inc. on CVD Graphene based product developments, we believe we can shorten the time to market for a range of already existing and future nano enabled products. Together, we are able to offer and ship a growing array of CVD Graphene products. Our initial product variety has already been supplied to our first customers.
Under this Agreement CVD Equipment Corporation will manufacture CVD grown Graphene based materials and products and Graphene Laboratories, Inc. will market and sell them on a worldwide basis.
CVD Equipment’s Application Laboratory provides process development and material growth services for a wide range of advanced nanomaterials, i.e., Carbon Nanotubes, Silicon and other Nanowires, CVD Graphene, Transparent Conducting Oxide (TCO) materials and other CVD processes. It hosts a range of CVD research and production equipment that will be utilized for CVD Graphene production.
Graphene is a novel nanomaterial carbon film that is only a few atoms thick and possesses unparalleled electrical and mechanical properties as well as supreme stability and durability.
CVD grown Graphene is projected to be used for production of Graphene-based electronics, sensors, MEMS, solar batteries, etc. Some of the CVD Graphene products sold by Graphene Laboratories Inc. will be marked with one or more trademarks from CVD Equipment, such as nMEMStarter, nFoil, and CVDGraphene.
“The ability to mass produce CVD Graphene is a key milestone for Graphene commercialization,” said Dr. Elena Polyakova, CEO of Graphene Laboratories.
“Currently, the progress in development of Graphene-based commercial products is largely stalled by a lack of supply of high-quality wafer-size Graphene films. CVD grown Graphene is well positioned to address this market demand. We anticipate strong interest from academic and industrial customers in our CVD Graphene products and this is an extremely important partnership for our Company. By selecting CVD Equipment Corporation as our partner, we will be able to expand our Graphene based product offerings and greatly advance the development of various Graphene enabled products.”
"CVD Equipment is focusing on enabling the commercialization of tomorrow’s technologies,” says Karlheinz Strobl, VP of Business Development of CVD Equipment.
“By leveraging the process development and manufacturing capabilities of our Application Laboratory and by collaborating with Graphene Laboratories Inc. on CVD Graphene based product developments, we believe we can shorten the time to market for a range of already existing and future nano enabled products. Together, we are able to offer and ship a growing array of CVD Graphene products. Our initial product variety has already been supplied to our first customers.
JDSU adds one-way delay test feature to T-BERD(R)/MTS-6000A
MILPITAS, USA: JDSU introduced the first field-portable solution for "one-way delay" testing. An enhancement to the T-BERD/MTS-6000A Multi-Services Application Module (MSAM), the solution provides measurement accuracy 10 times greater than most service level agreements (SLAs) currently require for Ethernet Backhaul and mission-critical applications.
This new feature helps to measure and troubleshoot service delay in networks that carry real-time voice, video and data services in Ethernet backhaul applications, as well as services in government and financial networks.
The JDSU One-Way Delay test feature enables providers to measure the delay of Ethernet, Internet Protocol version 4 (IPv4) and IPv6 traffic. This is critical for industries with real-time applications such as Voice over IP (VOIP), in which delay causes unacceptable quality issues, and financial transactions that depend on nearly instantaneous transmissions.
"One-way delay is a common factor in the degradation of voice, video and data service quality and reliability," said Mirna Mekic, director in JDSU's Communications Test and Measurement business segment.
"The JDSU One-Way Delay test feature for the T-BERD/MTS-6000A MSAM gives those responsible for network operations a simple and accurate method to perform a critical one-way SLA delay measurement that can characterize network performance. This unique feature provides valuable information useful in network turn-up and troubleshooting so that carriers can assure SLAs and optimize their networks to enhance quality of service."
JDSU's T-BERD/MTS-6000A MSAM is the industry's most compact multi-function tester. It supports the installation and maintenance of Carrier Ethernet and Internet Protocol (IP) services while also having the ability to simultaneously test Fiber Channel, Optical Transport Network (OTN), NextGen, Synchronous Optical Network (SONET/SDH) and legacy Time Division Multiplex (TDM) protocols all in one rugged, handheld unit.
This new feature helps to measure and troubleshoot service delay in networks that carry real-time voice, video and data services in Ethernet backhaul applications, as well as services in government and financial networks.
The JDSU One-Way Delay test feature enables providers to measure the delay of Ethernet, Internet Protocol version 4 (IPv4) and IPv6 traffic. This is critical for industries with real-time applications such as Voice over IP (VOIP), in which delay causes unacceptable quality issues, and financial transactions that depend on nearly instantaneous transmissions.
"One-way delay is a common factor in the degradation of voice, video and data service quality and reliability," said Mirna Mekic, director in JDSU's Communications Test and Measurement business segment.
"The JDSU One-Way Delay test feature for the T-BERD/MTS-6000A MSAM gives those responsible for network operations a simple and accurate method to perform a critical one-way SLA delay measurement that can characterize network performance. This unique feature provides valuable information useful in network turn-up and troubleshooting so that carriers can assure SLAs and optimize their networks to enhance quality of service."
JDSU's T-BERD/MTS-6000A MSAM is the industry's most compact multi-function tester. It supports the installation and maintenance of Carrier Ethernet and Internet Protocol (IP) services while also having the ability to simultaneously test Fiber Channel, Optical Transport Network (OTN), NextGen, Synchronous Optical Network (SONET/SDH) and legacy Time Division Multiplex (TDM) protocols all in one rugged, handheld unit.
Infineon and Elpida settle legal dispute
NEUBIBERG, GERMANY: Infineon Technologies AG recently announced that it has settled its patent infringement claim against Elpida Memory Inc., and both Infineon and Elpida have agreed to seek dismissal of all pending patent infringement cases.
Infineon initiated proceedings in February 2010, when it filed a complaint against Elpida and Elpida’s customers in the US International Trade Commission (ITC). Elpida subsequently filed two lawsuits in the US District Court, Eastern District of Virginia.
Infineon and Elpida have settled the dispute through a broad patent cross license relating to semiconductor technology. The specific terms and conditions of the license are confidential.
“Infineon is pleased to have reached this agreement with Elpida, and we look forward to a lasting peace between the companies,” said Prof. Dr. Hermann Eul, Member of the Management Board, responsible for Sales, Marketing, Technology and R&D at Infineon Technologies AG. “This outcome is further affirmation of our ongoing efforts to protect our intellectual property rights and business interests.”
Infineon initiated proceedings in February 2010, when it filed a complaint against Elpida and Elpida’s customers in the US International Trade Commission (ITC). Elpida subsequently filed two lawsuits in the US District Court, Eastern District of Virginia.
Infineon and Elpida have settled the dispute through a broad patent cross license relating to semiconductor technology. The specific terms and conditions of the license are confidential.
“Infineon is pleased to have reached this agreement with Elpida, and we look forward to a lasting peace between the companies,” said Prof. Dr. Hermann Eul, Member of the Management Board, responsible for Sales, Marketing, Technology and R&D at Infineon Technologies AG. “This outcome is further affirmation of our ongoing efforts to protect our intellectual property rights and business interests.”
Oclaro accelerates 100 Gbps coherent product development through alliance with ClariPhy
SAN JOSE, USA: Oclaro Inc., a tier-one provider of innovative optical communications and laser solutions, announced it has made a $7.5 million strategic investment in ClariPhy Communications, a privately-held fabless semiconductor company focused on digital signal processing (DSP) and mixed-signal integrated circuits (ICs) for high-speed next-generation networks.
In addition, ClariPhy and Oclaro have signed a Co-Marketing and Development Agreement leveraging ClariPhy's industry-leading 40nm, single-chip products with Oclaro's optical technology. The alliance with ClariPhy is an important milestone in Oclaro's strategy to build upon its leadership position in 40 Gigabits per second regional and metro networks and expand into the 100 Gb/s Coherent long-haul and ultra-long-haul markets.
The surge in new broadband services, such as social networking, video sharing, voice over IP (VoIP) and cloud computing, is creating significant demand for increased bandwidth and improved network performance, with global IP traffic expected to grow at a 40 percent CAGR between 2008 and 2013.
This intensive growth is driving the rapid transition from 10 Gb/s optical networks to 40 Gb/s and beyond. These very high bit rate communications require not only advanced optical solutions but also advanced DSP and mixed-signal integrated circuits, combined into modules for deployment by telecommunications systems providers. In particular, the move to 100 Gb/s requires Coherent technology, which is fundamental to extending the reach of high-speed networks.
"We expect an increasing percentage of the transceiver solutions for optical networks to be comprised of DSP and mixed-signal electronics as they evolve towards 40 Gb/s and 100 Gb/s," stated Alain Couder, President and CEO, Oclaro.
"Through our investment and alliance with ClariPhy, Oclaro believes it will be able to offer its customers best-in-class electronics and optical technology as a complete solution from a single source, whether incorporated directly in our Oclaro solutions, or co-marketed as complementary products."
Oclaro is a market leader in the 40 Gb/s market, with a leading market-share position in regional and metro networks. In the Differential Quadrature Phase Shift Keying (DQPSK) and Differential Phase Shift Keying (DPSK) space for regional and first-generation long-haul markets respectively, Oclaro already offers Lithium Niobate (LiNbO3) and Indium Phosphide (InP) component solutions.
At the sub-system level, the Oclaro vertical-integration model has resulted in ground-breaking technology disruption, as demonstrated by Oclaro's fully-qualified 40 Gb/s DQPSK 300-pin transponder solution for regional and metro applications. From this base, Oclaro is now looking to broaden its high bit rate portfolio into next-generation long-haul and ultra-long haul with coherent detection methodology.
With the standardization of 100 Gb/s gaining momentum, Oclaro believes it will continue to deliver these core optical building blocks, alongside ClariPhy's world-class signal processing engines, and to provide best-in-class module solutions.
"By leveraging the significant 40nm CMOS technology innovation from ClariPhy, Oclaro will focus on optimizing our future optical products to further increase bandwidth, improve network performance, and lower the total cost of ownership for customers," added Couder.
Oclaro and ClariPhy have a history of collaboration and offer products that have been designed to improve the performance and bandwidth of optical networks. With an industry-leading low power dissipation, Oclaro's TL9000M small form factor 300-pin transponder for 10 Gb/s networks, announced in 2009 and containing ClariPhy's maximum likelihood sequence estimation (MLSE) IC, established a new benchmark in transmission performance for dispersion-tolerant modules.
Oclaro's 300-pin transponder portfolio continues to ramp and take market share in the 10 Gb/s space. Oclaro is now taking this to the next level by driving a product strategy to deliver technology-disruptive transceivers such as Tunable XFP and XFP+, which when combined with ClariPhy's IC, is believed to deliver the industry's highest-density, lowest-power MLSE-based solution.
Oclaro and ClariPhy believe that the ongoing combination of the companies' advanced optics and signal processing delivers the performance and integration the market demands for these next generation 10 Gb/s modules.
"We are delighted to enter into a strategic alliance with Oclaro," said Dr. Paul Voois, co-founder and CEO of ClariPhy. "This alliance brings together industry-leading mixed-signal CMOS technology from ClariPhy with the world-class optical technology from Oclaro. By working together to deliver innovative solutions to the market, Oclaro and ClariPhy can help customers accelerate deployment of the next generation of high-speed networks."
In addition, ClariPhy and Oclaro have signed a Co-Marketing and Development Agreement leveraging ClariPhy's industry-leading 40nm, single-chip products with Oclaro's optical technology. The alliance with ClariPhy is an important milestone in Oclaro's strategy to build upon its leadership position in 40 Gigabits per second regional and metro networks and expand into the 100 Gb/s Coherent long-haul and ultra-long-haul markets.
The surge in new broadband services, such as social networking, video sharing, voice over IP (VoIP) and cloud computing, is creating significant demand for increased bandwidth and improved network performance, with global IP traffic expected to grow at a 40 percent CAGR between 2008 and 2013.
This intensive growth is driving the rapid transition from 10 Gb/s optical networks to 40 Gb/s and beyond. These very high bit rate communications require not only advanced optical solutions but also advanced DSP and mixed-signal integrated circuits, combined into modules for deployment by telecommunications systems providers. In particular, the move to 100 Gb/s requires Coherent technology, which is fundamental to extending the reach of high-speed networks.
"We expect an increasing percentage of the transceiver solutions for optical networks to be comprised of DSP and mixed-signal electronics as they evolve towards 40 Gb/s and 100 Gb/s," stated Alain Couder, President and CEO, Oclaro.
"Through our investment and alliance with ClariPhy, Oclaro believes it will be able to offer its customers best-in-class electronics and optical technology as a complete solution from a single source, whether incorporated directly in our Oclaro solutions, or co-marketed as complementary products."
Oclaro is a market leader in the 40 Gb/s market, with a leading market-share position in regional and metro networks. In the Differential Quadrature Phase Shift Keying (DQPSK) and Differential Phase Shift Keying (DPSK) space for regional and first-generation long-haul markets respectively, Oclaro already offers Lithium Niobate (LiNbO3) and Indium Phosphide (InP) component solutions.
At the sub-system level, the Oclaro vertical-integration model has resulted in ground-breaking technology disruption, as demonstrated by Oclaro's fully-qualified 40 Gb/s DQPSK 300-pin transponder solution for regional and metro applications. From this base, Oclaro is now looking to broaden its high bit rate portfolio into next-generation long-haul and ultra-long haul with coherent detection methodology.
With the standardization of 100 Gb/s gaining momentum, Oclaro believes it will continue to deliver these core optical building blocks, alongside ClariPhy's world-class signal processing engines, and to provide best-in-class module solutions.
"By leveraging the significant 40nm CMOS technology innovation from ClariPhy, Oclaro will focus on optimizing our future optical products to further increase bandwidth, improve network performance, and lower the total cost of ownership for customers," added Couder.
Oclaro and ClariPhy have a history of collaboration and offer products that have been designed to improve the performance and bandwidth of optical networks. With an industry-leading low power dissipation, Oclaro's TL9000M small form factor 300-pin transponder for 10 Gb/s networks, announced in 2009 and containing ClariPhy's maximum likelihood sequence estimation (MLSE) IC, established a new benchmark in transmission performance for dispersion-tolerant modules.
Oclaro's 300-pin transponder portfolio continues to ramp and take market share in the 10 Gb/s space. Oclaro is now taking this to the next level by driving a product strategy to deliver technology-disruptive transceivers such as Tunable XFP and XFP+, which when combined with ClariPhy's IC, is believed to deliver the industry's highest-density, lowest-power MLSE-based solution.
Oclaro and ClariPhy believe that the ongoing combination of the companies' advanced optics and signal processing delivers the performance and integration the market demands for these next generation 10 Gb/s modules.
"We are delighted to enter into a strategic alliance with Oclaro," said Dr. Paul Voois, co-founder and CEO of ClariPhy. "This alliance brings together industry-leading mixed-signal CMOS technology from ClariPhy with the world-class optical technology from Oclaro. By working together to deliver innovative solutions to the market, Oclaro and ClariPhy can help customers accelerate deployment of the next generation of high-speed networks."
ST's newest 3-axis accelerometer: Stingy with power, spendthrift with features
GENEVA, SWITZERLAND: STMicroelectronics has extended its motion-sensor portfolio with a 3-axis digital-output accelerometer that combines a drastically reduced power consumption – more than 90% lower than available solutions on the market - with miniature footprint and enhanced functionality.
With operating current consumption as low as 2 microamps, the 3x3x1 mm accelerometer is a perfect fit for motion-sensing features and applications in space- and power-constrained consumer devices, such as mobile phones, remotes and game controllers.
The sensor provides extremely accurate output across full-scale ranges of + or - 2g/+
or - 4g/+ or - 8g/+ or - 16g, boasting excellent stability over time and temperature.
The LIS3DH accelerometer contains a temperature sensor and three analog-to-digital converter channels for easy integration with companion chips, such as gyroscopes.
It embeds a host of enhanced features, including click and double-click recognition, 4D/6D orientation detection, and the power-saving sleep-to-wake-up mode. In this mode, the device keeps the read chain active and wakes up when an event occurs, automatically increasing the output data rate.
Other important features include a programmable FIFO (first-in first-out) memory block and two programmable interrupt signals that enable immediate notification of motion detection, click/double-click events, and other conditions.
The latest addition in ST's MEMS portfolio, the LIS3DH has been designed and produced using the same manufacturing-process technology that ST has already successfully applied to more than 700 million motion sensors sold in the market.
The device is pin-to-pin and software-compatible with all ST accelerometers in the LIS331 family, so customers can easily 'hot swap' and protect their investment in application development.
Volume production is scheduled for early Q3 2010 and the unit price is $0.85 in quantities of 100,000 units.
With operating current consumption as low as 2 microamps, the 3x3x1 mm accelerometer is a perfect fit for motion-sensing features and applications in space- and power-constrained consumer devices, such as mobile phones, remotes and game controllers.
The sensor provides extremely accurate output across full-scale ranges of + or - 2g/+
or - 4g/+ or - 8g/+ or - 16g, boasting excellent stability over time and temperature.
The LIS3DH accelerometer contains a temperature sensor and three analog-to-digital converter channels for easy integration with companion chips, such as gyroscopes.
It embeds a host of enhanced features, including click and double-click recognition, 4D/6D orientation detection, and the power-saving sleep-to-wake-up mode. In this mode, the device keeps the read chain active and wakes up when an event occurs, automatically increasing the output data rate.
Other important features include a programmable FIFO (first-in first-out) memory block and two programmable interrupt signals that enable immediate notification of motion detection, click/double-click events, and other conditions.
The latest addition in ST's MEMS portfolio, the LIS3DH has been designed and produced using the same manufacturing-process technology that ST has already successfully applied to more than 700 million motion sensors sold in the market.
The device is pin-to-pin and software-compatible with all ST accelerometers in the LIS331 family, so customers can easily 'hot swap' and protect their investment in application development.
Volume production is scheduled for early Q3 2010 and the unit price is $0.85 in quantities of 100,000 units.
ClariPhy announces $24 million investment, new strategic alliances
IRVINE, USA: ClariPhy Communications, a leader in ultra high speed mixed signal, digital signal processing (MXSP) integrated circuits for optical networks, has secured $24M in series C funding.
The financing includes new strategic investors -- Oclaro, Inc., a tier-one provider of optical communications and laser components, and multiple telecom OEMs. All ClariPhy's existing venture investors participated in this round, including Norwest Venture Partners, Allegis Capital, ONSET Ventures, and Pacific General Partners.
ClariPhy will use the funding to deliver a new class of single chip MXSP ICs that significantly increase an optical network's reach and tolerance to impairments (such as chromatic dispersion, polarization mode dispersion and fiber nonlinearity), while reducing cost of ownership for both OEMs and Service Providers.
The company's line of 10G, 40G and 100G networking chips are based on advanced MXSP schemes such as Maximum Likelihood Sequence Estimation (MLSE) and Coherent Detection that approach the limits of achievable performance.
ClariPhy's implementation of these schemes in 40 nm single-chip CMOS enables equipment designers to reduce cost and power by integrating multiple system functions into customized System on Chip (SoC) solutions.
Driving demand for these MXSP ICs is the growing adoption of a variety of new broadband services from video and social networking to voice-over-IP and cloud computing. With analysts predicting that network traffic will grow by more than 40% annually over the next five years, network operators are rapidly migrating from 10G to 40G transmission rates and beyond.
"We are honored to have such a quality group of investors participate in our financing," said Dr. Paul Voois, cofounder and CEO of ClariPhy. "As transmission rates increase, network equipment designers need low-cost, low-power solutions that extend reach and minimize signal impairment across high performance networks. This funding will enable us to deliver the MXSP technology that addresses their needs. Our new partnerships with Oclaro and others open up exciting opportunities to gain insight into customer problems, integrate our innovative technology into new ASIC and SoC applications, and generate significant new revenue streams."
The financing includes new strategic investors -- Oclaro, Inc., a tier-one provider of optical communications and laser components, and multiple telecom OEMs. All ClariPhy's existing venture investors participated in this round, including Norwest Venture Partners, Allegis Capital, ONSET Ventures, and Pacific General Partners.
ClariPhy will use the funding to deliver a new class of single chip MXSP ICs that significantly increase an optical network's reach and tolerance to impairments (such as chromatic dispersion, polarization mode dispersion and fiber nonlinearity), while reducing cost of ownership for both OEMs and Service Providers.
The company's line of 10G, 40G and 100G networking chips are based on advanced MXSP schemes such as Maximum Likelihood Sequence Estimation (MLSE) and Coherent Detection that approach the limits of achievable performance.
ClariPhy's implementation of these schemes in 40 nm single-chip CMOS enables equipment designers to reduce cost and power by integrating multiple system functions into customized System on Chip (SoC) solutions.
Driving demand for these MXSP ICs is the growing adoption of a variety of new broadband services from video and social networking to voice-over-IP and cloud computing. With analysts predicting that network traffic will grow by more than 40% annually over the next five years, network operators are rapidly migrating from 10G to 40G transmission rates and beyond.
"We are honored to have such a quality group of investors participate in our financing," said Dr. Paul Voois, cofounder and CEO of ClariPhy. "As transmission rates increase, network equipment designers need low-cost, low-power solutions that extend reach and minimize signal impairment across high performance networks. This funding will enable us to deliver the MXSP technology that addresses their needs. Our new partnerships with Oclaro and others open up exciting opportunities to gain insight into customer problems, integrate our innovative technology into new ASIC and SoC applications, and generate significant new revenue streams."
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