BANGALORE, INDIA: Analog Devices, Inc. (ADI), a global leader in high-performance semiconductors for signal-processing applications and leading supplier of high-performance amplifiers, introduced the dual version of its popular ADA4898-1 operational amplifier (op amp).
Like the ADA4898-1, the ADA4898-2 dual-channel, high-speed op amp offers designers a unique blend of the low distortion, ultra-low noise and high speed effective for applications that require high precision signal processing, such as radar-based collision avoidance systems in cars, medical instrumentation, process control and industrial automation and other precision instrumentation applications.
The dual channel version reduces the size of the packaging while maintaining performance. The amplifier is designed to work with Analog Devices’ precision data converters, including the 18-bit, differential programmable input PulSAR® ADCs (analog-to-digital converters), the AD7631 and AD7634.
Wednesday, February 3, 2010
Arasan offers complete line of memory card controller IP cores and software stacks
SAN JOSE, USA: Arasan Chip Systems Inc., a leading provider of Total IP Solutions to enable the rapid adoption of emerging technologies, announced today the availability of a complete portfolio of Memory Card Controller IP cores and corresponding software stacks.
These card controller IP support the highest performance card formats: Secure Digital (SD/SDIO 3.0), Multimedia Card (e.MMC 4.4), Memory Stick (MSPro, MSPro-Duo), CompactFlash (CF+) and Picture Card (xD) card formats.
The rapid growth of portable media players, megapixel DSC, smartphones, netbooks and gaming consoles has led to the proliferation of removable non-volatile memory cards - both to store and distribute content. Aided by the rapid advances in NAND memory technology, these compact cards are now common accessories to consumer electronics.
Makers of host devices need to decide which formats to support in order to ease consumer adoption of their hardware. Consumers on the other hand, would like these devices to be memory card agnostic.
System designers of chipsets and application processor thus need to optimize their controller architecture based on the usage model and form-factor of the final end-device.
For example, applications requiring higher levels of security and boot capability might rely on a combination of SD and e.MMC controllers, while those requiring frequent insertion and removal might also add support for the larger CompactFlash cards. Arasan enables designers to make such optimizations by offering a complete range of Memory Card controllers IP cores in different combinations.
"System designers seek an optimal balance between the number of card formats to support versus the implementation costs," said Prakash Kamath, Vice-President of Engineering at Arasan. "Now, with the availability of Arasan's Memory Card Controller family of IP, they can select the right combination of card controller IP suitable for their system design and usage model."
Arasan's Memory Card Controller IP cores support the latest versions of SD, SDIO, e.MMC, MSPro, MSPro-Duo, CF+ and xD in multiple configurations. Arasan provides a Total IP Solution for each of these cores - comprising of Digital IP, verification IP, Software stacks and Hardware Development kits backed by World-class customer support.
Commenting on the card controller software stacks that are part of the Total Solutions, Atul Garg, Director of Software Engineering at Arasan said, "A well architected memory controller software stack is crucial to realizing the performance and capacity benefits of these memory cards. We have developed these software stacks based on our in-depth understanding of the nuances of these memory interfaces and have optimized the stacks to ease porting to alternate OS and processor platforms."
These card controller IP support the highest performance card formats: Secure Digital (SD/SDIO 3.0), Multimedia Card (e.MMC 4.4), Memory Stick (MSPro, MSPro-Duo), CompactFlash (CF+) and Picture Card (xD) card formats.
The rapid growth of portable media players, megapixel DSC, smartphones, netbooks and gaming consoles has led to the proliferation of removable non-volatile memory cards - both to store and distribute content. Aided by the rapid advances in NAND memory technology, these compact cards are now common accessories to consumer electronics.
Makers of host devices need to decide which formats to support in order to ease consumer adoption of their hardware. Consumers on the other hand, would like these devices to be memory card agnostic.
System designers of chipsets and application processor thus need to optimize their controller architecture based on the usage model and form-factor of the final end-device.
For example, applications requiring higher levels of security and boot capability might rely on a combination of SD and e.MMC controllers, while those requiring frequent insertion and removal might also add support for the larger CompactFlash cards. Arasan enables designers to make such optimizations by offering a complete range of Memory Card controllers IP cores in different combinations.
"System designers seek an optimal balance between the number of card formats to support versus the implementation costs," said Prakash Kamath, Vice-President of Engineering at Arasan. "Now, with the availability of Arasan's Memory Card Controller family of IP, they can select the right combination of card controller IP suitable for their system design and usage model."
Arasan's Memory Card Controller IP cores support the latest versions of SD, SDIO, e.MMC, MSPro, MSPro-Duo, CF+ and xD in multiple configurations. Arasan provides a Total IP Solution for each of these cores - comprising of Digital IP, verification IP, Software stacks and Hardware Development kits backed by World-class customer support.
Commenting on the card controller software stacks that are part of the Total Solutions, Atul Garg, Director of Software Engineering at Arasan said, "A well architected memory controller software stack is crucial to realizing the performance and capacity benefits of these memory cards. We have developed these software stacks based on our in-depth understanding of the nuances of these memory interfaces and have optimized the stacks to ease porting to alternate OS and processor platforms."
NXP brings HDMI 1.4 to mobile phones
SINGAPORE: NXP Semiconductors announced a new HDMI 1.4 transmitter solution, TDA19989, which enables consumers to transfer HD multimedia content from their mobile phones directly to a television via the TV remote control.
The TDA19989 features ultra-low power consumption, a small form factor, and support of full HD (1080i/p). The device supports the newly introduced HDMI 1.4 Type D micro-connector and provides an additional embedded Consumer Electronic Control feature, which enables users to control their mobile phones through their TV remotes.
With the explosion of high-definition (HD) multimedia content, it is common for devices to support 10M pixels+ camera sensors. HD content support is becoming one of the major criteria when selecting a mobile phone or electronic devices.
In addition, with over 90 percent HDMI attachment rate on TV, the integration of HDMI on PC platforms, and the wide adoption on HD digital camcorders and cameras, HDMI is the “must-have” HD video and audio interface that enables 100 percent interoperability for portable companions with displays.
“With its tiny footprint and support for the newly introduced HDMI 1.4 Type D micro-connector, the TDA19989 HDMI transmitter is the ideal solution for bringing the HDMI interface to mobile phones. Broad market support for full HD makes it easier to transfer content with no loss from a mobile phone to a television display,” said Patrick Lejoly, marketing and system architecture manager, Product Line Media Interfaces, NXP Semiconductors.
“NXP has also reduced the HDMI low-power transmitter budget to sub-100mW, allowing for more than 7 hours’ HD video streaming on battery via HDMI. In addition, the introduction of this new interface is a key element for Open Source developers to leverage HD availability on mobile phones.”
To further reduce BOM cost and ease of design, the TDA 19989 provides additional embedded features such as CEC (Consumer Electronic Control). This feature eliminates the need of any additional device to handle CEC and enables CEC-connected devices to be controlled by only one remote control.
NXP worked on a Zoom OMAP34x-II mobile development platform (MDP) from Texas Instruments (TI) to demonstrate the Consumer Electronic Control (CEC) feature. The Zoom OMAP34x-II MDP is based on TI’s proven OMAP3430 applications processor.
Fred Cohen, director of the OMAP wireless ecosystem at TI, said: “The CEC feature takes ease of use to the next level by allowing the control of portable electronic devices, such as mobile phones, through existing TV remote controls. Sitting on a couch, for example, a user can play, stop or fast forward a movie on an HD phone connected through HDMI to an HD TV. This capability brings new use cases to the mobile market, and helps consumers connect to their phones and other consumer electronic devices in a whole new way.”
The TDA19989 features ultra-low power consumption, a small form factor, and support of full HD (1080i/p). The device supports the newly introduced HDMI 1.4 Type D micro-connector and provides an additional embedded Consumer Electronic Control feature, which enables users to control their mobile phones through their TV remotes.
With the explosion of high-definition (HD) multimedia content, it is common for devices to support 10M pixels+ camera sensors. HD content support is becoming one of the major criteria when selecting a mobile phone or electronic devices.
In addition, with over 90 percent HDMI attachment rate on TV, the integration of HDMI on PC platforms, and the wide adoption on HD digital camcorders and cameras, HDMI is the “must-have” HD video and audio interface that enables 100 percent interoperability for portable companions with displays.
“With its tiny footprint and support for the newly introduced HDMI 1.4 Type D micro-connector, the TDA19989 HDMI transmitter is the ideal solution for bringing the HDMI interface to mobile phones. Broad market support for full HD makes it easier to transfer content with no loss from a mobile phone to a television display,” said Patrick Lejoly, marketing and system architecture manager, Product Line Media Interfaces, NXP Semiconductors.
“NXP has also reduced the HDMI low-power transmitter budget to sub-100mW, allowing for more than 7 hours’ HD video streaming on battery via HDMI. In addition, the introduction of this new interface is a key element for Open Source developers to leverage HD availability on mobile phones.”
To further reduce BOM cost and ease of design, the TDA 19989 provides additional embedded features such as CEC (Consumer Electronic Control). This feature eliminates the need of any additional device to handle CEC and enables CEC-connected devices to be controlled by only one remote control.
NXP worked on a Zoom OMAP34x-II mobile development platform (MDP) from Texas Instruments (TI) to demonstrate the Consumer Electronic Control (CEC) feature. The Zoom OMAP34x-II MDP is based on TI’s proven OMAP3430 applications processor.
Fred Cohen, director of the OMAP wireless ecosystem at TI, said: “The CEC feature takes ease of use to the next level by allowing the control of portable electronic devices, such as mobile phones, through existing TV remote controls. Sitting on a couch, for example, a user can play, stop or fast forward a movie on an HD phone connected through HDMI to an HD TV. This capability brings new use cases to the mobile market, and helps consumers connect to their phones and other consumer electronic devices in a whole new way.”
Electric vehicles driving up semiconductor demand
UK: Electric vehicles have been the stars of recent motor shows. Vehicle manufacturers have been at pains to demonstrate how hybrid and battery electric vehicles are a big part of their development plans. This all bodes well for semiconductor suppliers. The value of semiconductors in electric vehicles is much greater than in vehicles with conventional engines.
A new report* from IMS Research forecasts that demand for electric vehicles will grow steadily throughout the decade ahead from less than 600,000 in 2008 to over 12 million in 2020.
Some vehicle manufacturers already offer hybrid electric vehicles. Many others have plans to introduce them, while commercially viable plug-in hybrid and battery electric vehicles are just staring to emerge. Governments around the world are investing money to support the development efforts of the vehicle manufacturers. The Chevrolet Volt, Nissan Leaf and BMW Mini EV are just some of the high profile models expected to enter production in 2010.
From a semiconductor supplier’s point of view, growing production volumes of electric vehicles are only one side of the equation. The other side is that the value of semiconductors in an electric vehicle drivetrain is not only higher than in a conventional vehicle drivetrain: according to the IMS Research report, it is over 10 times higher!
Power devices account for much of this increased semiconductor content. According to report author, Jon Cropley: “These vehicles have significant power IC, power discrete and power module content. Much of this is for the inverter required to drive the vehicle’s main motor/generators. However, many other electric vehicle drivetrain applications require semiconductors including battery monitoring and control, DC/DC converters, AC/DC chargers and air conditioning converters.”
Many semiconductor suppliers have so far found it difficult to enter the supply chain for electric vehicles. Japanese vehicle manufacturers have dominated production and have either used their own semiconductors or used semiconductors from suppliers they part own (Keiretsu partners). These barriers to market entry look set to disappear as vehicle manufacturers from other regions ramp up production and Japanese vehicle manufacturers look for competing semiconductor vendors.
As is always the case with automotive applications, semiconductors for electric vehicles must meet demanding performance requirements and must been keenly priced. However, according to the IMS Research report, the market could be worth over $7 billion in 2020. As world economies struggle to recover from the recent economic downturn, this developing market could provide suppliers with a rare opportunity for substantial growth.
A new report* from IMS Research forecasts that demand for electric vehicles will grow steadily throughout the decade ahead from less than 600,000 in 2008 to over 12 million in 2020.
Some vehicle manufacturers already offer hybrid electric vehicles. Many others have plans to introduce them, while commercially viable plug-in hybrid and battery electric vehicles are just staring to emerge. Governments around the world are investing money to support the development efforts of the vehicle manufacturers. The Chevrolet Volt, Nissan Leaf and BMW Mini EV are just some of the high profile models expected to enter production in 2010.
From a semiconductor supplier’s point of view, growing production volumes of electric vehicles are only one side of the equation. The other side is that the value of semiconductors in an electric vehicle drivetrain is not only higher than in a conventional vehicle drivetrain: according to the IMS Research report, it is over 10 times higher!
Power devices account for much of this increased semiconductor content. According to report author, Jon Cropley: “These vehicles have significant power IC, power discrete and power module content. Much of this is for the inverter required to drive the vehicle’s main motor/generators. However, many other electric vehicle drivetrain applications require semiconductors including battery monitoring and control, DC/DC converters, AC/DC chargers and air conditioning converters.”
Many semiconductor suppliers have so far found it difficult to enter the supply chain for electric vehicles. Japanese vehicle manufacturers have dominated production and have either used their own semiconductors or used semiconductors from suppliers they part own (Keiretsu partners). These barriers to market entry look set to disappear as vehicle manufacturers from other regions ramp up production and Japanese vehicle manufacturers look for competing semiconductor vendors.
As is always the case with automotive applications, semiconductors for electric vehicles must meet demanding performance requirements and must been keenly priced. However, according to the IMS Research report, the market could be worth over $7 billion in 2020. As world economies struggle to recover from the recent economic downturn, this developing market could provide suppliers with a rare opportunity for substantial growth.
Cadence Encounter Digital Implementation System 9.1 addresses productivity crisis for complex SoC design
SAN JOSE, USA: Cadence Design Systems Inc. has released Cadence Encounter Digital Implementation (EDI) System 9.1, a complete and integrated digital design, implementation, and verification environment for the development of large-scale, complex SoCs.
The new and expanded suite of capabilities in EDI System 9.1 answers the industry call for improved designer productivity in developing advanced low power and mixed signal SoCs at leading-edge process nodes – such as 32- and 28-nanometer -- with hundreds of millions of gates, including hundreds of IP elements and embedded processors.
Consumer demand for smaller, faster, feature-rich devices drives demand for larger-scale, higher-performance and lower-power SoCs. To compete in these markets, semiconductor companies must deliver the best and most differentiated designs, faster than the competition—a tricky combination that forces semiconductor companies to work through conflicting design objectives and sometimes incur higher manufacturing costs or take on greater technology and business risks.
EDI System 9.1 removes these challenges to design productivity through innovative design exploration capabilities. By combining automatic floorplan synthesis, unique data abstraction modeling, and new concurrent macro- and standard cell placement, all driven by fully the embedded signoff analysis capabilities of EDI System, users can quickly find and implement the optimal physical architecture of a chip.
Design exploration does this by automatically and concurrently examining thousands of combinations of design variables, option settings, floorplan architectures, and physical implementation approaches in parallel. This exhaustive examination allows users to fully explore the range of design possibilities, and deliver smaller, faster, higher functioning chips, while accelerating design schedules by weeks or months.
EDI System also improves designer productivity by broadening its integrated suite of native signoff capabilities. Building on its existing foundry certified power, timing, and signal integrity (SI) signoff capabilities, EDI System 9.1 now adds silicon-accurate extraction and design-for-manufacturing (DFM) analyses to complete the picture.
The new integrated, turbo QRC extraction capability provides fast in-design, incremental signoff extraction and drives fast and convergent design closure for physical and electrical design requirements. Also, since foundries now mandate DFM checks in the physical design flow at 40-nanometer and below, built-in, foundry-certified DFM analysis is a must-have at these nodes.
The new integrated DFM capability –turbo Litho Physical Analyzer – brings built-in litho pattern intelligence and filtering to the interconnect routing phase, enabling automatic detection, prevention, and correction of potential litho hotspots before they happen. This capability improves DFM and yield for advanced 40-, 32- and 28-nanometer nodes and is significantly faster than traditional lithography signoff tools.
EDI System 9.1 also extends its innovative memory architecture to achieve significant gains in memory capacity, acceleration in single-CPU operations, and improved performance scalability across its multi-CPU backplane, bringing efficient parallel processing throughout the design flow.
The convergence of design exploration, signoff-driven implementation, faster performance, and larger capacity in EDI System 9.1 has a significant impact to designer productivity. It enables designers to design, implement, and verify chips 2-3X larger and 2X faster than traditional flows and with superior quality of silicon. The tight integration of signoff checks in the implementation phase enables exceptional correlation to final silicon, thereby reducing the potential for expensive silicon respins.
“Our 10GBASE-T PHYs are tuned for the highest performance and lowest power on the smallest die area,” said Sridhar Begur, vice president of engineering at Teranetics. “With EDI System’s end-to-end multi-CPU timing closure solution, we were able to reduce our turnaround time by more than half, and meet our design objectives significantly ahead of schedule. EDI System also provided us with an advanced 40-nanometer flow, enabling accurate, in-design prevention and fixing of lithography effects that translated to increased manufacturability and yield of our designs.”
The constant pursuit of excellence in semiconductor design leads to a stream of technology advancements and fundamental shifts in design methodologies and processes to better manage SoC complexity, improve quality of silicon, and to ensure chips get to market on time. Silicon-on-insulator (SOI), high-k metal gates, and 3D-IC/through-silicon via (TSV) are just a few examples of some of these shifts taking place.
In addition, a growing list of advanced low power design techniques such as dual flip-flop, pulse latch, power switch optimization and hierarchical low power design are being explored and employed by companies seeking the utmost in power reduction. Cadence, in collaboration with leading semiconductor companies and ecosystem partners, continues to play a pivotal role in driving the definition, development, and enablement for these areas, and EDI System 9.1 is a prime example of where it all comes together.
“Semiconductor leaders and ecosystem partners provide us with early insight into emerging challenges, and this collaboration is exactly what allows us to get ahead of the curve,” said David Desharnais, group director of design, implementation and verification product management at Cadence.
“The compounding complexities of chip design and the economics associated with bringing a SoC to market, drive a renewed interest in closing the productivity gap and achieving chip profitability as quickly as possible. The new EDI System 9.1 release provides the industry with the capability to achieve those goals.”
The new and expanded suite of capabilities in EDI System 9.1 answers the industry call for improved designer productivity in developing advanced low power and mixed signal SoCs at leading-edge process nodes – such as 32- and 28-nanometer -- with hundreds of millions of gates, including hundreds of IP elements and embedded processors.
Consumer demand for smaller, faster, feature-rich devices drives demand for larger-scale, higher-performance and lower-power SoCs. To compete in these markets, semiconductor companies must deliver the best and most differentiated designs, faster than the competition—a tricky combination that forces semiconductor companies to work through conflicting design objectives and sometimes incur higher manufacturing costs or take on greater technology and business risks.
EDI System 9.1 removes these challenges to design productivity through innovative design exploration capabilities. By combining automatic floorplan synthesis, unique data abstraction modeling, and new concurrent macro- and standard cell placement, all driven by fully the embedded signoff analysis capabilities of EDI System, users can quickly find and implement the optimal physical architecture of a chip.
Design exploration does this by automatically and concurrently examining thousands of combinations of design variables, option settings, floorplan architectures, and physical implementation approaches in parallel. This exhaustive examination allows users to fully explore the range of design possibilities, and deliver smaller, faster, higher functioning chips, while accelerating design schedules by weeks or months.
EDI System also improves designer productivity by broadening its integrated suite of native signoff capabilities. Building on its existing foundry certified power, timing, and signal integrity (SI) signoff capabilities, EDI System 9.1 now adds silicon-accurate extraction and design-for-manufacturing (DFM) analyses to complete the picture.
The new integrated, turbo QRC extraction capability provides fast in-design, incremental signoff extraction and drives fast and convergent design closure for physical and electrical design requirements. Also, since foundries now mandate DFM checks in the physical design flow at 40-nanometer and below, built-in, foundry-certified DFM analysis is a must-have at these nodes.
The new integrated DFM capability –turbo Litho Physical Analyzer – brings built-in litho pattern intelligence and filtering to the interconnect routing phase, enabling automatic detection, prevention, and correction of potential litho hotspots before they happen. This capability improves DFM and yield for advanced 40-, 32- and 28-nanometer nodes and is significantly faster than traditional lithography signoff tools.
EDI System 9.1 also extends its innovative memory architecture to achieve significant gains in memory capacity, acceleration in single-CPU operations, and improved performance scalability across its multi-CPU backplane, bringing efficient parallel processing throughout the design flow.
The convergence of design exploration, signoff-driven implementation, faster performance, and larger capacity in EDI System 9.1 has a significant impact to designer productivity. It enables designers to design, implement, and verify chips 2-3X larger and 2X faster than traditional flows and with superior quality of silicon. The tight integration of signoff checks in the implementation phase enables exceptional correlation to final silicon, thereby reducing the potential for expensive silicon respins.
“Our 10GBASE-T PHYs are tuned for the highest performance and lowest power on the smallest die area,” said Sridhar Begur, vice president of engineering at Teranetics. “With EDI System’s end-to-end multi-CPU timing closure solution, we were able to reduce our turnaround time by more than half, and meet our design objectives significantly ahead of schedule. EDI System also provided us with an advanced 40-nanometer flow, enabling accurate, in-design prevention and fixing of lithography effects that translated to increased manufacturability and yield of our designs.”
The constant pursuit of excellence in semiconductor design leads to a stream of technology advancements and fundamental shifts in design methodologies and processes to better manage SoC complexity, improve quality of silicon, and to ensure chips get to market on time. Silicon-on-insulator (SOI), high-k metal gates, and 3D-IC/through-silicon via (TSV) are just a few examples of some of these shifts taking place.
In addition, a growing list of advanced low power design techniques such as dual flip-flop, pulse latch, power switch optimization and hierarchical low power design are being explored and employed by companies seeking the utmost in power reduction. Cadence, in collaboration with leading semiconductor companies and ecosystem partners, continues to play a pivotal role in driving the definition, development, and enablement for these areas, and EDI System 9.1 is a prime example of where it all comes together.
“Semiconductor leaders and ecosystem partners provide us with early insight into emerging challenges, and this collaboration is exactly what allows us to get ahead of the curve,” said David Desharnais, group director of design, implementation and verification product management at Cadence.
“The compounding complexities of chip design and the economics associated with bringing a SoC to market, drive a renewed interest in closing the productivity gap and achieving chip profitability as quickly as possible. The new EDI System 9.1 release provides the industry with the capability to achieve those goals.”
Linde intros line of dopant gas sources for IC manufacturers
MURRAY HILL, USA: For semiconductor manufacturers looking for a sub-atmospheric dopant gas source that will deliver high performance at a lower cost, Linde North America has the answer: the Genii Sub-Atmospheric Gas Sources.
Linde North America is a member of The Linde Group, a world leading gases and engineering group and a major supplier of high-purity gases and technology to the semiconductor and electronics manufacturing industries. The new Linde ion implantation gas sources use chemical complexing or electrochemical generation as a means to achieve the desired performance characteristics required by integrated circuit (IC) manufacturers.
Ion implantation is a critical step in the manufacture of integrated circuits. It is the method of introducing doping gases such as arsine, phosphine and boron trifluoride, to the silicon substrate. IC manufacturers prefer using dopants in sub-atmospheric pressure cylinders because of the inherent safety compared with higher pressure alternatives.
“The Genii Sub-Atmospheric Gas Sources from Linde provide IC manufacturers with a lower cost-of-ownership, high-performance alternative to other sub-atmospheric products currently on the market,” said Peter Thomas, vice president of marketing for Linde’s electronics business.
Beta testing at an IC maker’s site proved that the Genii gas sources can reduce a manufacturer’s ion implant source costs by a minimum of 20 percent with no impact on device performance.
Linde is offering two technologies in the Genii dopant line. One generates arsine at sub-atmospheric pressure from an electrochemical generator housed in the cylinder. The second delivers enriched boron trifluoride or phosphine through chemical complexing with ionic liquids contained in the cylinder.
“Both technologies deliver the kind of performance and efficiencies IC manufacturers require,” Thomas said. “And they are a demonstration of Linde’s ongoing commitment to developing new products for the electronics industry,” he said.
The Linde Group is a world leading gases and engineering company with almost 50,000 employees working in around 100 countries worldwide. In the 2008 financial year it achieved sales of EUR 12.7 billion (USD 15.9 billion). The strategy of The Linde Group is geared towards sustainable earnings-based growth and focuses on the expansion of its international business with forward-looking products and services.
Linde North America is a member of The Linde Group, a world leading gases and engineering group and a major supplier of high-purity gases and technology to the semiconductor and electronics manufacturing industries. The new Linde ion implantation gas sources use chemical complexing or electrochemical generation as a means to achieve the desired performance characteristics required by integrated circuit (IC) manufacturers.
Ion implantation is a critical step in the manufacture of integrated circuits. It is the method of introducing doping gases such as arsine, phosphine and boron trifluoride, to the silicon substrate. IC manufacturers prefer using dopants in sub-atmospheric pressure cylinders because of the inherent safety compared with higher pressure alternatives.
“The Genii Sub-Atmospheric Gas Sources from Linde provide IC manufacturers with a lower cost-of-ownership, high-performance alternative to other sub-atmospheric products currently on the market,” said Peter Thomas, vice president of marketing for Linde’s electronics business.
Beta testing at an IC maker’s site proved that the Genii gas sources can reduce a manufacturer’s ion implant source costs by a minimum of 20 percent with no impact on device performance.
Linde is offering two technologies in the Genii dopant line. One generates arsine at sub-atmospheric pressure from an electrochemical generator housed in the cylinder. The second delivers enriched boron trifluoride or phosphine through chemical complexing with ionic liquids contained in the cylinder.
“Both technologies deliver the kind of performance and efficiencies IC manufacturers require,” Thomas said. “And they are a demonstration of Linde’s ongoing commitment to developing new products for the electronics industry,” he said.
The Linde Group is a world leading gases and engineering company with almost 50,000 employees working in around 100 countries worldwide. In the 2008 financial year it achieved sales of EUR 12.7 billion (USD 15.9 billion). The strategy of The Linde Group is geared towards sustainable earnings-based growth and focuses on the expansion of its international business with forward-looking products and services.
austriamicrosystems expands reliance on Cadence technology to achieve seamless mixed-signal SoC designs
FELDKIRCHEN, GERMANY: Cadence Design Systems Inc. announced that austriamicrosystems, a leading global designer and manufacturer of high-performance analog ICs for communications, industrial, medical and automotive applications and foundry services, has broadened its deployment of Cadence technology.
Over the last two decades, austriamicrosystems has relied on the Cadence Virtuoso custom IC design platform for its analog and mixed-signal designs and process design kits (PDKs). By choosing Cadence Encounter Digital Implementation System for the digital part of its designs, the company can now ensure a tight integration between its design flows.
“austriamicrosystems has used Cadence technology for the development and manufacturing of our analog ICs since 1992. To handle the digital parts of our mixed-signal system-on-chip designs, it was crucial for us to collaborate with one of the most experienced EDA suppliers in this space,” said Thomas Riener, Vice President and General Manager BU Full Service Foundry, at austriamicrosystems. “With Cadence Encounter Digital Implementation System, we are now enabled to tightly integrate our design flows, which will enable us further in ensuring our customers’ success."
Encounter Digital Implementation System is a full-featured leading-edge digital implementation solution that offers tight interoperability between analog and digital design environments for mixed-signal implementation and analysis. It also delivers the unique ability to perform top-level static timing analysis for mixed-signal designs, including digital components within the analog hierarchy.
Cadence design-for-manufacturing (DFM) technologies are an integral part of the EDI System, enabling early identification, analysis and repair of yield-limiting design elements present at advanced nodes.
“A solution that shares a unified database between custom and digital implementation offers a vast advantage for our customers,” said Limin He, vice president Research & Development of IC digital products at Cadence. “austriamicrosystems benefits from the enhanced interoperability, which enables better communication between the design teams. That enables austriamicrosystems to deploy a more efficient design flow and to save precious design time.”
Over the last two decades, austriamicrosystems has relied on the Cadence Virtuoso custom IC design platform for its analog and mixed-signal designs and process design kits (PDKs). By choosing Cadence Encounter Digital Implementation System for the digital part of its designs, the company can now ensure a tight integration between its design flows.
“austriamicrosystems has used Cadence technology for the development and manufacturing of our analog ICs since 1992. To handle the digital parts of our mixed-signal system-on-chip designs, it was crucial for us to collaborate with one of the most experienced EDA suppliers in this space,” said Thomas Riener, Vice President and General Manager BU Full Service Foundry, at austriamicrosystems. “With Cadence Encounter Digital Implementation System, we are now enabled to tightly integrate our design flows, which will enable us further in ensuring our customers’ success."
Encounter Digital Implementation System is a full-featured leading-edge digital implementation solution that offers tight interoperability between analog and digital design environments for mixed-signal implementation and analysis. It also delivers the unique ability to perform top-level static timing analysis for mixed-signal designs, including digital components within the analog hierarchy.
Cadence design-for-manufacturing (DFM) technologies are an integral part of the EDI System, enabling early identification, analysis and repair of yield-limiting design elements present at advanced nodes.
“A solution that shares a unified database between custom and digital implementation offers a vast advantage for our customers,” said Limin He, vice president Research & Development of IC digital products at Cadence. “austriamicrosystems benefits from the enhanced interoperability, which enables better communication between the design teams. That enables austriamicrosystems to deploy a more efficient design flow and to save precious design time.”
Tuesday, February 2, 2010
Semiconductor Policy 2010 unveiled by Govt. of Karnataka in association with ISA
BANGALORE, INDIA: The India Semiconductor Association (ISA) along with the IT Department, Government of Karnataka today announced the semiconductor policy for Karnataka.
Hon’ble Chief Minister of Karnataka, B.S. Yeddyurappa and Hon’ble IT and BT Minister, Katta Subramanya Naidu, along with B.V. Naidu, chairman, ISA, and chairman and CEO, Sagitaur Ventures India Pvt Ltd and other dignitaries unveiled the policy.
B.V. Naidu, Chairman ISA Chairman and CEO, Sagitaur Ventures India Pvt. Ltd, said: “ISA welcomes the Karnataka Semicon Policy and we are happy that most of our recommendations to the government have been considered and this policy will play a significant role for achieving $120 billion electronic system design and manufacturing industry to grow in Karnataka. Announcement of the semiconductor policy is the first of its kind in India and reflects the spirit of Government to continue its growth in the country."
Rajiv Kapur, managing director, Broadcom India, said: “ISA is pleased to see Karnataka show leadership by recognizing the opportunity available to take the industry to the next level. This policy is the first of its kind coming from a state government of India and will play a big role in stimulating growth.”
S. Janakiraman, president and Group CEO, Product Engineering Services, MindTree, said: “Karnataka has been a hub for electronics and embedded software for the last few decades. Now the time has come to focus on semiconductors, which are an important part of the value chain. The new policy by the Karnataka government will accelerate the pace of investment in the semiconductor sector. We, as ISA and MindTree, are excited about the support we are receiving from the government.”
Pradip Dutta, ISA Vision Summit 2010 convener and corporate vice president and managing director, Synopsys, said: “The ISA has been working very closely with the state government of Karnataka to draft the semiconductor policy for the last 12 months. At the same time, the ISA has also initiated a policy on electronic system design and manufacturing with Dept of IT, Government of India. While the national target is to reach $400 billion by 2020, Karnataka alone aims to contribute 30 percent of the national target, which is close to $120 billion. We see a strong synergy between the national objectives and the Karnataka Policy. We are all very optimistic, that this will also attract additional investment in the region.”
Jaswinder Ahuja, corporate vice president and managing director, Cadence Design Systems (I) Pvt Ltd: said "Karnataka is India’s semiconductor hub and it is laudable that the Karnataka Government has taken a proactive step to encourage the industry in the form of the semiconductor policy announced today. The Government’s policy is a step in the right direction and takes a balanced view of the various aspects of electronics system design and manufacturing. In particular, the funds announced to provide seed funding to semiconductor, solar and ATMP entrepreneurs will give a fillip to startups setting up projects in the state.
He further added: “A great strength for India, especially Karnataka, is its qualified manpower in the form of engineering graduates. The semiconductor school in conjunction with IIIT is encouraging as it will enable the industry by training fresh graduates to be industry-ready. Encouraging semiconductor excellence in the state is also praiseworthy. While the Rs 10 crore fund allocated towards this is a good first step, the cap of Rs 10 lakh per unit for R&D expenses is limiting. The tax exemptions and incentives for companies that invest in large projects in the state are positive."
Janardhana Swamy (Member of Parliament from Chittradurga) also graced the conference. Swamy, who has over 15 years of experience in the semiconductor, EDA and computing industries, emphasized the need of bridging the gap between industry and government. Industry leaders appreciated Swamy for being a role model for the professional youth.
Hon’ble Chief Minister of Karnataka, B.S. Yeddyurappa and Hon’ble IT and BT Minister, Katta Subramanya Naidu, along with B.V. Naidu, chairman, ISA, and chairman and CEO, Sagitaur Ventures India Pvt Ltd and other dignitaries unveiled the policy.B.V. Naidu, Chairman ISA Chairman and CEO, Sagitaur Ventures India Pvt. Ltd, said: “ISA welcomes the Karnataka Semicon Policy and we are happy that most of our recommendations to the government have been considered and this policy will play a significant role for achieving $120 billion electronic system design and manufacturing industry to grow in Karnataka. Announcement of the semiconductor policy is the first of its kind in India and reflects the spirit of Government to continue its growth in the country."
Rajiv Kapur, managing director, Broadcom India, said: “ISA is pleased to see Karnataka show leadership by recognizing the opportunity available to take the industry to the next level. This policy is the first of its kind coming from a state government of India and will play a big role in stimulating growth.”
S. Janakiraman, president and Group CEO, Product Engineering Services, MindTree, said: “Karnataka has been a hub for electronics and embedded software for the last few decades. Now the time has come to focus on semiconductors, which are an important part of the value chain. The new policy by the Karnataka government will accelerate the pace of investment in the semiconductor sector. We, as ISA and MindTree, are excited about the support we are receiving from the government.”
Pradip Dutta, ISA Vision Summit 2010 convener and corporate vice president and managing director, Synopsys, said: “The ISA has been working very closely with the state government of Karnataka to draft the semiconductor policy for the last 12 months. At the same time, the ISA has also initiated a policy on electronic system design and manufacturing with Dept of IT, Government of India. While the national target is to reach $400 billion by 2020, Karnataka alone aims to contribute 30 percent of the national target, which is close to $120 billion. We see a strong synergy between the national objectives and the Karnataka Policy. We are all very optimistic, that this will also attract additional investment in the region.”
Jaswinder Ahuja, corporate vice president and managing director, Cadence Design Systems (I) Pvt Ltd: said "Karnataka is India’s semiconductor hub and it is laudable that the Karnataka Government has taken a proactive step to encourage the industry in the form of the semiconductor policy announced today. The Government’s policy is a step in the right direction and takes a balanced view of the various aspects of electronics system design and manufacturing. In particular, the funds announced to provide seed funding to semiconductor, solar and ATMP entrepreneurs will give a fillip to startups setting up projects in the state.
He further added: “A great strength for India, especially Karnataka, is its qualified manpower in the form of engineering graduates. The semiconductor school in conjunction with IIIT is encouraging as it will enable the industry by training fresh graduates to be industry-ready. Encouraging semiconductor excellence in the state is also praiseworthy. While the Rs 10 crore fund allocated towards this is a good first step, the cap of Rs 10 lakh per unit for R&D expenses is limiting. The tax exemptions and incentives for companies that invest in large projects in the state are positive."
Janardhana Swamy (Member of Parliament from Chittradurga) also graced the conference. Swamy, who has over 15 years of experience in the semiconductor, EDA and computing industries, emphasized the need of bridging the gap between industry and government. Industry leaders appreciated Swamy for being a role model for the professional youth.
NetLogic intros world’s first knowledge-based processor with high-speed serial interface
MOUNTAIN VIEW, USA: NetLogic Microsystems Inc. has announced the NL111024 processor, the world’s first knowledge-based processor with high-speed serial interface, and a member of its sixth-generation knowledge-based processor family.
The integration of high-speed serial interface delivers 225Gbps of raw chip-to-chip interconnect bandwidth. This represents a 340% increase in I/O bandwidth-per-pin to enable significantly higher system performance, higher system density and lower system costs for next-generation systems to enable significantly richer services for LTE, IPTV and IPv6 services. In addition, the NL111024 processor features an enhanced knowledge-based processing core capable of achieving 1.6 billion decisions per second (BDPS).
The exponential growth in network services and applications for next-generation LTE and IPTV deployments are driving the need for increased classification and security processing per packet. This is in turn driving the need for higher performance knowledge-based processors with high-speed serial links to significantly enhance the interconnect bandwidth and communications between the knowledge-based processors and system packet processors such as multi-core processors, network processors and customer ASICs.
In addition, the migration from IPv4 to IPv6 is resulting in 4x wider addresses for Layers 2-4 processing. This translates into the need for higher I/O bandwidth and larger knowledge database density and capacity. The higher I/O bandwidth of the NL111024 processor delivers an improved balance between the knowledge-based processing core and the I/O performance to allow wider IPv6 keys to be processed at the same search rate as narrower IPv4 keys.
In addition to the higher I/O bandwidth, the narrow-bus differential signaling of the NL111024 processor’s high-speed serial interface also enables customers to develop system boards with a lower layer count, thereby reducing the complexity and costs of next-generation systems.
“Our NL111024 knowledge-based processor is truly revolutionary as it is designed and optimized to meet and exceed the needs of our customers who are looking to simultaneously support much richer services and IPv6 capabilities,” said Chris O’Reilly, vice president of marketing at NetLogic Microsystems.
“By raising the bar on the knowledge-based processing performance to 1.6BDPS and enhancing the I/O bandwidth by 340 percent, this NL111024 device showcases the true R&D cross-development synergies within the company as it brings together our industry-leading knowledge-based processing technology with our best-in-class PHY and SerDes technology.”
In addition to featuring the high-speed serial link, the NL111024 processor is a fully-programmable “hybrid” knowledge-based processor that features the convergence of high-performance, massively parallel knowledge-based processing with the low-power efficiency and flexibility of algorithmic Sahasra technology to dramatically reduce power consumption while delivering best-in-class performance and functionality.
The processor integrates 128 high-performance knowledge-based processing engines, and includes an enhanced Intelligent Load Balancing Engine (ILBE) to efficiently allocate multiple tasks and communicate among all the 128 knowledge-based processing engines. The knowledge-based processing engines and ILBE are tightly coupled with integrated advanced Sahasra Algorithmic Engines (SAEs) to dramatically lower the power consumption of search processing.
The NL111024 knowledge-based processor also integrates an innovative Range Encoding Engine (REE), which employs advanced one-hot and fence encoding algorithms to implement range encoding that allows customers to effectively double the efficiency of performing port range inspection.
The integration of high-speed serial interface delivers 225Gbps of raw chip-to-chip interconnect bandwidth. This represents a 340% increase in I/O bandwidth-per-pin to enable significantly higher system performance, higher system density and lower system costs for next-generation systems to enable significantly richer services for LTE, IPTV and IPv6 services. In addition, the NL111024 processor features an enhanced knowledge-based processing core capable of achieving 1.6 billion decisions per second (BDPS).
The exponential growth in network services and applications for next-generation LTE and IPTV deployments are driving the need for increased classification and security processing per packet. This is in turn driving the need for higher performance knowledge-based processors with high-speed serial links to significantly enhance the interconnect bandwidth and communications between the knowledge-based processors and system packet processors such as multi-core processors, network processors and customer ASICs.
In addition, the migration from IPv4 to IPv6 is resulting in 4x wider addresses for Layers 2-4 processing. This translates into the need for higher I/O bandwidth and larger knowledge database density and capacity. The higher I/O bandwidth of the NL111024 processor delivers an improved balance between the knowledge-based processing core and the I/O performance to allow wider IPv6 keys to be processed at the same search rate as narrower IPv4 keys.
In addition to the higher I/O bandwidth, the narrow-bus differential signaling of the NL111024 processor’s high-speed serial interface also enables customers to develop system boards with a lower layer count, thereby reducing the complexity and costs of next-generation systems.
“Our NL111024 knowledge-based processor is truly revolutionary as it is designed and optimized to meet and exceed the needs of our customers who are looking to simultaneously support much richer services and IPv6 capabilities,” said Chris O’Reilly, vice president of marketing at NetLogic Microsystems.
“By raising the bar on the knowledge-based processing performance to 1.6BDPS and enhancing the I/O bandwidth by 340 percent, this NL111024 device showcases the true R&D cross-development synergies within the company as it brings together our industry-leading knowledge-based processing technology with our best-in-class PHY and SerDes technology.”
In addition to featuring the high-speed serial link, the NL111024 processor is a fully-programmable “hybrid” knowledge-based processor that features the convergence of high-performance, massively parallel knowledge-based processing with the low-power efficiency and flexibility of algorithmic Sahasra technology to dramatically reduce power consumption while delivering best-in-class performance and functionality.
The processor integrates 128 high-performance knowledge-based processing engines, and includes an enhanced Intelligent Load Balancing Engine (ILBE) to efficiently allocate multiple tasks and communicate among all the 128 knowledge-based processing engines. The knowledge-based processing engines and ILBE are tightly coupled with integrated advanced Sahasra Algorithmic Engines (SAEs) to dramatically lower the power consumption of search processing.
The NL111024 knowledge-based processor also integrates an innovative Range Encoding Engine (REE), which employs advanced one-hot and fence encoding algorithms to implement range encoding that allows customers to effectively double the efficiency of performing port range inspection.
TriQuint announces TriPower -- high-power family of 'green' base station amplifier RF transistors
BARCELONA, SPAIN & HILLSBORO, USA: TriQuint Semiconductor, a leading RF products manufacturer and foundry services provider, has released the first products in its new, high-efficiency ‘green’ TriPower family of 3G/4G wireless base station RFICs.
TriPower devices allow network operators to address the top two challenges of rapidly-growing consumer demand for bandwidth-hungry smartphones and similar products. TriPower reduces electricity needed to power network base station amplifiers while it allows operators to more easily increase network capacity and speed.
A more efficient amplifier translates into real savings. Imagine a system with 2,000 such amplifiers as might be used to cover one medium-sized city and surrounding area. Comparing the efficiency of TriPower to what’s typically deployed today, a TriPower-based network would cut CO2 emissions by about 340 tons each year.
According to the US Forestry Service, each acre of trees absorbs about 2.6 tons of CO2 annually. Using TriPower in such a system would be the equivalent of adding more than 130 acres of trees to the ecosystem.
“TriPower is a revolutionary advance for base station amplifiers,” said TriQuint Networks Vice President, Brian P. Balut.
“The complex modulation requirements of 3G and 4G networks cannot be delivered efficiently by legacy semiconductor technologies. As a leader in both GaAs and GaN (Gallium Nitride) technology, TriQuint examined the potential for both types of devices in high-power base station applications. We believe that for reasons of reliability, cost and efficiency, TriPower’s GaAs HV-HBT technology is the best choice. Our new TriPower devices provide the greatest reduction in power consumption available on the market today and can enable new, highly-efficient, tower-mounted remote radio head designs. TriPower is game-changing technology.”
Balut explained that TriQuint employs proprietary process, design and manufacturing techniques to achieve TriPower’s outstanding efficiency performance. TriPower RFICs can be easily linearized using conventional Digital Pre-Distortion (DPD) techniques, he added.
“We believe that any technology that can increase overall efficiency of the RF power amplifier, such as TriPower from TriQuint, will allow the industry to meet the more stringent energy requirements for high PAR (Peak to Average Ratio) amplifiers going forward,” said Earl J. Lum, President of EJL Wireless Research LLC.
“We forecast that through 2013, higher PAR multi-mode 3G WCDMA / HSPA and 4G LTE base stations will rapidly replace legacy 2G GSM for BTS (base transceiver station) shipments and will increase in market share from 25 percent to over 50 percent of the market. On a unit basis, shipments of high PAR amplifiers for base stations will dramatically increase 85 percent on an annual basis from 2008 through 2013.”
Independent researchers at the University of California at San Diego have compared key base station amplifier semiconductor technologies including Silicon LDMOS, Gallium Nitride (GaN) and TriPower GaAs HV-HBT technology. UCSD lead researcher, Professor Donald Kimball, concluded in a paper published in November 20081 that TriPower devices offer a clear efficiency advantage.
“There has been a vigorous competition between different transistor technologies for the highest efficiency in base station amplifiers. TriQuint’s HV-HBT has clearly come out on top,” remarked Prof. Kimball. “HV-HBT is the greenest device for base station radios. It will make a significant difference for power reduction in future systems, including ones in remote areas with limited prime power availability.”
TriPower devices allow network operators to address the top two challenges of rapidly-growing consumer demand for bandwidth-hungry smartphones and similar products. TriPower reduces electricity needed to power network base station amplifiers while it allows operators to more easily increase network capacity and speed.
A more efficient amplifier translates into real savings. Imagine a system with 2,000 such amplifiers as might be used to cover one medium-sized city and surrounding area. Comparing the efficiency of TriPower to what’s typically deployed today, a TriPower-based network would cut CO2 emissions by about 340 tons each year.
According to the US Forestry Service, each acre of trees absorbs about 2.6 tons of CO2 annually. Using TriPower in such a system would be the equivalent of adding more than 130 acres of trees to the ecosystem.
“TriPower is a revolutionary advance for base station amplifiers,” said TriQuint Networks Vice President, Brian P. Balut.
“The complex modulation requirements of 3G and 4G networks cannot be delivered efficiently by legacy semiconductor technologies. As a leader in both GaAs and GaN (Gallium Nitride) technology, TriQuint examined the potential for both types of devices in high-power base station applications. We believe that for reasons of reliability, cost and efficiency, TriPower’s GaAs HV-HBT technology is the best choice. Our new TriPower devices provide the greatest reduction in power consumption available on the market today and can enable new, highly-efficient, tower-mounted remote radio head designs. TriPower is game-changing technology.”
Balut explained that TriQuint employs proprietary process, design and manufacturing techniques to achieve TriPower’s outstanding efficiency performance. TriPower RFICs can be easily linearized using conventional Digital Pre-Distortion (DPD) techniques, he added.
“We believe that any technology that can increase overall efficiency of the RF power amplifier, such as TriPower from TriQuint, will allow the industry to meet the more stringent energy requirements for high PAR (Peak to Average Ratio) amplifiers going forward,” said Earl J. Lum, President of EJL Wireless Research LLC.
“We forecast that through 2013, higher PAR multi-mode 3G WCDMA / HSPA and 4G LTE base stations will rapidly replace legacy 2G GSM for BTS (base transceiver station) shipments and will increase in market share from 25 percent to over 50 percent of the market. On a unit basis, shipments of high PAR amplifiers for base stations will dramatically increase 85 percent on an annual basis from 2008 through 2013.”
Independent researchers at the University of California at San Diego have compared key base station amplifier semiconductor technologies including Silicon LDMOS, Gallium Nitride (GaN) and TriPower GaAs HV-HBT technology. UCSD lead researcher, Professor Donald Kimball, concluded in a paper published in November 20081 that TriPower devices offer a clear efficiency advantage.
“There has been a vigorous competition between different transistor technologies for the highest efficiency in base station amplifiers. TriQuint’s HV-HBT has clearly come out on top,” remarked Prof. Kimball. “HV-HBT is the greenest device for base station radios. It will make a significant difference for power reduction in future systems, including ones in remote areas with limited prime power availability.”
Monday, February 1, 2010
Global chip sales decline 9 percent in 2009; total sales of $226.3 billion above expectations
SAN JOSE, USA: The Semiconductor Industry Association (SIA) today reported that worldwide semiconductor sales in 2009 were $226.3 billion, a decline of 9 percent from 2008 when sales were $248.6 billion.
Total sales for 2009 surpassed the SIA forecast of $219.7 billion. December sales were $22.4 billion, an increase of 29 percent from December 2008, when sales were $17.4 billion. December sales declined by 1.2 percent from November when sales were $22.7 billion. All monthly sales numbers represent a three-month moving average.
“2009 turned out to be a better year for the global semiconductor industry than expected,” said SIA President George Scalise. “A strong focus on inventories throughout the supply chain mitigated the impact of the worldwide economic downturn and positioned the industry for growth as the global economy recovers.
“Sales in the final quarter of 2009 were supported by healthy demand in a variety of end markets including PCs, cell phones, and consumer electronics. In 2010, unit sales of personal computers and cell phones – which account for approximately 60 percent of total semiconductor consumption – will grow in the low-to-mid teens, providing a solid platform for chip sales. Consumer electronics are expected to grow in the mid-single digits,” Scalise continued.
“We are also seeing the effects of recovery in the enterprise sector and we believe this trend will continue,” Scalise noted. SIA expects a return to normal seasonal patterns, which suggests a modest slowdown in the first quarter.
China and India, two key emerging markets, are also driving demand. In addition to purchasing consumer items such as handsets and computers, both regions are continuing to invest in wired and wireless infrastructure. These investments in infrastructure create demand for a broad range of semiconductor products.
“Advances in technology are continually enabling development of new products, such as netbook and tablet computers,” said Scalise. “Attractive price points for these products are creating new market segments that hadn’t previously existed, and they are adding to overall semiconductor demand.
“With improving consumer confidence and signs of economic recovery around the world, the semiconductor industry is well positioned for growth in 2010,” Scalise concluded.
Source: Semiconductor Industry Association (SIA)
Total sales for 2009 surpassed the SIA forecast of $219.7 billion. December sales were $22.4 billion, an increase of 29 percent from December 2008, when sales were $17.4 billion. December sales declined by 1.2 percent from November when sales were $22.7 billion. All monthly sales numbers represent a three-month moving average.“2009 turned out to be a better year for the global semiconductor industry than expected,” said SIA President George Scalise. “A strong focus on inventories throughout the supply chain mitigated the impact of the worldwide economic downturn and positioned the industry for growth as the global economy recovers.
“Sales in the final quarter of 2009 were supported by healthy demand in a variety of end markets including PCs, cell phones, and consumer electronics. In 2010, unit sales of personal computers and cell phones – which account for approximately 60 percent of total semiconductor consumption – will grow in the low-to-mid teens, providing a solid platform for chip sales. Consumer electronics are expected to grow in the mid-single digits,” Scalise continued.
“We are also seeing the effects of recovery in the enterprise sector and we believe this trend will continue,” Scalise noted. SIA expects a return to normal seasonal patterns, which suggests a modest slowdown in the first quarter.
China and India, two key emerging markets, are also driving demand. In addition to purchasing consumer items such as handsets and computers, both regions are continuing to invest in wired and wireless infrastructure. These investments in infrastructure create demand for a broad range of semiconductor products.
“Advances in technology are continually enabling development of new products, such as netbook and tablet computers,” said Scalise. “Attractive price points for these products are creating new market segments that hadn’t previously existed, and they are adding to overall semiconductor demand.
“With improving consumer confidence and signs of economic recovery around the world, the semiconductor industry is well positioned for growth in 2010,” Scalise concluded.
Source: Semiconductor Industry Association (SIA)
Altera unveils innovations for 28-nm FPGAs
SAN JOSE, USA: Building on its history of technology leadership, Altera Corp. announced tnew innovations that will be incorporated into upcoming 28-nm FPGAs. Embedded HardCopy Blocks, a new method for partial reconfiguration and embedded 28-Gbps transceivers will dramatically improve the density and I/O performance of next-generation Altera FPGAs and further strengthen their competitive position versus ASICs and ASSPs.
The rapid growth of bandwidth-intensive applications such as high-definition (HD) video, cloud computing, online data storage and mobile video has created a challenge for both infrastructure and end-user equipment developers. How can they quickly increase system bandwidth while staying within strict power and cost budgets? Altera has developed its latest innovations to solve these challenges.
The new Embedded HardCopy Blocks are customizable hard intellectual property (IP) blocks that leverage Altera’s unique HardCopy ASIC capabilities. They are used to harden standard or logic-intensive functions such as interface protocols, application-specific functions, and proprietary custom IP.
The Embedded HardCopy Blocks offer customers faster time to market for their designs while also reducing cost and power. For Altera, this innovation allows the company to quickly create variant products and target specific market segments.
Partial reconfiguration allows designers to reconfigure part of the FPGA while other sections remain running. This is extremely important in systems where uptime is critical because it allows designers to make updates or adjust functionality without disrupting services.
Lowering power and cost, partial reconfiguration also improves effective logic density by removing the necessity to place in the FPGA functions that do not operate simultaneously. Instead, these functions can be stored in external memory and loaded as needed. This reduces the size of the FPGA by allowing multiple applications on a single FPGA, saving board space and reducing power.
To date, partial reconfiguration solutions have been time-intensive tasks that required designers to know all of the intricate FPGA architecture details. Altera is simplifying the partial reconfiguration process by building the capability on top of the proven incremental compile design flow in its Quartus II design software.
Extending its leadership in embedded transceiver technology, Altera has developed 28-Gbps embedded transceivers, which will also be implemented in upcoming 28-nm FPGAs. These high-speed transceivers will enable customers to implement next-generation designs such as 400G systems on a single chip without the need for costly external components.
"Two years ago, Altera introduced the industry's first 40-nm FPGAs, and continued delivering industry firsts such as embedded 11.3-Gbps transceivers," said John Daane, president, chairman and CEO of Altera. "As we move to the next process node, these new innovations from Altera will take the industry beyond the benefits of Moore's Law to solve bandwidth challenges while staying within cost and power requirements."
The rapid growth of bandwidth-intensive applications such as high-definition (HD) video, cloud computing, online data storage and mobile video has created a challenge for both infrastructure and end-user equipment developers. How can they quickly increase system bandwidth while staying within strict power and cost budgets? Altera has developed its latest innovations to solve these challenges.
The new Embedded HardCopy Blocks are customizable hard intellectual property (IP) blocks that leverage Altera’s unique HardCopy ASIC capabilities. They are used to harden standard or logic-intensive functions such as interface protocols, application-specific functions, and proprietary custom IP.
The Embedded HardCopy Blocks offer customers faster time to market for their designs while also reducing cost and power. For Altera, this innovation allows the company to quickly create variant products and target specific market segments.
Partial reconfiguration allows designers to reconfigure part of the FPGA while other sections remain running. This is extremely important in systems where uptime is critical because it allows designers to make updates or adjust functionality without disrupting services.
Lowering power and cost, partial reconfiguration also improves effective logic density by removing the necessity to place in the FPGA functions that do not operate simultaneously. Instead, these functions can be stored in external memory and loaded as needed. This reduces the size of the FPGA by allowing multiple applications on a single FPGA, saving board space and reducing power.
To date, partial reconfiguration solutions have been time-intensive tasks that required designers to know all of the intricate FPGA architecture details. Altera is simplifying the partial reconfiguration process by building the capability on top of the proven incremental compile design flow in its Quartus II design software.
Extending its leadership in embedded transceiver technology, Altera has developed 28-Gbps embedded transceivers, which will also be implemented in upcoming 28-nm FPGAs. These high-speed transceivers will enable customers to implement next-generation designs such as 400G systems on a single chip without the need for costly external components.
"Two years ago, Altera introduced the industry's first 40-nm FPGAs, and continued delivering industry firsts such as embedded 11.3-Gbps transceivers," said John Daane, president, chairman and CEO of Altera. "As we move to the next process node, these new innovations from Altera will take the industry beyond the benefits of Moore's Law to solve bandwidth challenges while staying within cost and power requirements."
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