MOUNTAIN VIEW, USA: Synopsys Inc. today announced the broad availability of silicon-proven High-Definition Multimedia Interface (HDMI) transmitter and receiver digital controllers and PHY IP solutions as part of Synopsys' DesignWare IP portfolio.
Synopsys' DesignWare IP for the HDMI interface is compliant to the standard specification and supports High-bandwidth Digital Content Protection (HDCP). Synopsys also provides a roadmap for HDMI 1.4 with product availability anticipated at the end of 2009.
The IP is available in leading process technologies from 90-nm down to 40-nm, and includes sample software drivers for system development. Synopsys' HDMI IP solution is differentiated in terms of feature set, available process nodes and worldwide technical support.
The DesignWare HDMI IP offering includes a comprehensive set of IP deliverables that helps designers quickly embed this complex interface into next generation multimedia SoCs with less risk. Furthermore, the DesignWare HDMI IP solution provides differentiated features including:
* Superior analog front end to support longer HDMI cables, while maintaining high performance.
* Configurable RTL allow designers to optimize gate count and power consumption by choosing only the features required in their application.
* Built-in (on-die) termination resistors for lower bill-of-materials.
* Numerous optional features as well as a choice of various video and audio interfaces for ease of integration.
"HDMI is one of fastest growing multimedia interfaces and is gaining wide-spread acceptance as the standard for communicating between high-performance digital devices," said Paul O'Donovan, principal analyst at Gartner.
"Our research indicates exponential growth in the number of HDMI ports for mobile/portable markets such as camcorders and cameras. HDMI IP will play a key role in enabling designers to integrate the HDMI interface in their next-generation systems."
"Valens continues to develop next generation products for the high definition home entertainment market, and we chose Synopsys to provide us with a high-quality, compliant HDMI IP solution that would help us quickly implement the latest functionality into our advanced SoCs," said Massad Eyal, vice president of research and development R&D at Valens Semiconductor.
"Synopsys' silicon-proven DesignWare HDMI IP enables us to deliver compelling products to the market faster and with significantly less risk."
"HDMI has emerged as the de-facto multimedia interface standard for high-definition consumer electronics and mobile devices," said John Koeter, vice president of marketing for the Solutions Group.
"With Synopsys' extensive customer base, established sales and support infrastructure, and vast porting capabilities, designers can turn to a trusted HDMI IP solution that can be integrated into their SoC with less risk and improved time-to-market."
The DesignWare HDMI 1.3 Transmit and Receive Controllers and PHY IP are available now in leading 90-nm, 65-nm, 45-nm, and 40-nm process technologies. The DesignWare HDMI 1.4 IP solution is currently in development and anticipated to be available at the end of 2009.
Showing posts with label DesignWare IP. Show all posts
Showing posts with label DesignWare IP. Show all posts
Thursday, August 13, 2009
Tuesday, July 21, 2009
Synopsys' DesignWare IP slashes power in datapath circuits
MOUNTAIN VIEW, USA: Synopsys Inc. announced the DesignWare minPower Components, a new IP product that is an integral part of the Synopsys Eclypse Low Power Solution.
The DesignWare minPower Components dramatically reduce power in datapath logic compared to traditional power optimization methods. By using the DesignWare minPower Components, leading wireless, networking and DSP companies achieved power reduction of up to 48 percent in datapath logic.
"Optimizing the power consumption of datapath circuits in mobile applications can significantly extend battery life because these blocks are often on, even in standby mode," said John Koeter, vice president of marketing for the Solutions Group at Synopsys. "Our customers have achieved an additional 7 to 48 percent reduction in power for these circuits."
"As the high speed networking market evolves to support another 10X increase in data rates, power dissipation has become an important issue in the adoption of next-generation technologies," said Jag Bolaria, senior analyst at The Linley Group.
"To be competitive, chip manufacturers need to optimize power dissipation in the datapath. Synopsys' DesignWare minPower Components include innovative techniques that address this problem - enabling designers to further reduce power consumption at advanced data rates."
Today's conventional techniques do not address reducing specific power elements such as glitch power in deep logic levels and dynamic power in high-performance datapath pipelines.
The DesignWare minPower Components offer unique, power-optimized datapath architectures that enable the DC Ultra synthesis tool to automatically generate circuits that suppress switching activity and glitches, reducing both dynamic and leakage power for mobile devices and high-performance applications.
Based on the actual switching activities, transition probabilities, available standard cells and analysis of possible configurations, the DesignWare minPower Components architectures are automatically configured by DC Ultra to implement the optimal structure with the lowest power consumption.
In addition to the automatically inferable components, the DesignWare minPower Components also include more than 40 instantiable components that incorporate low power design techniques such as enhanced clock gating, built-in datapath gating and patented data-tracking pipeline management technology to reduce power consumption.
The DesignWare minPower Components are tightly integrated with the Synopsys Galaxy Implementation Platform, which enables significant optimization of a design's total power compared to existing flows. The unique architectures in the DesignWare minPower Components allow high-level datapath structures to be automatically optimized based on power costing and switching activities.
Applications with datapath circuits that have a high percentage of active time, such as wireless receivers, audio/video processors, CPUs, media processors, and signal processing blocks for high-performance networking and storage, are ideal candidates for the DesignWare minPower Components.
The DesignWare minPower Components dramatically reduce power in datapath logic compared to traditional power optimization methods. By using the DesignWare minPower Components, leading wireless, networking and DSP companies achieved power reduction of up to 48 percent in datapath logic.
"Optimizing the power consumption of datapath circuits in mobile applications can significantly extend battery life because these blocks are often on, even in standby mode," said John Koeter, vice president of marketing for the Solutions Group at Synopsys. "Our customers have achieved an additional 7 to 48 percent reduction in power for these circuits."
"As the high speed networking market evolves to support another 10X increase in data rates, power dissipation has become an important issue in the adoption of next-generation technologies," said Jag Bolaria, senior analyst at The Linley Group.
"To be competitive, chip manufacturers need to optimize power dissipation in the datapath. Synopsys' DesignWare minPower Components include innovative techniques that address this problem - enabling designers to further reduce power consumption at advanced data rates."
Today's conventional techniques do not address reducing specific power elements such as glitch power in deep logic levels and dynamic power in high-performance datapath pipelines.
The DesignWare minPower Components offer unique, power-optimized datapath architectures that enable the DC Ultra synthesis tool to automatically generate circuits that suppress switching activity and glitches, reducing both dynamic and leakage power for mobile devices and high-performance applications.
Based on the actual switching activities, transition probabilities, available standard cells and analysis of possible configurations, the DesignWare minPower Components architectures are automatically configured by DC Ultra to implement the optimal structure with the lowest power consumption.
In addition to the automatically inferable components, the DesignWare minPower Components also include more than 40 instantiable components that incorporate low power design techniques such as enhanced clock gating, built-in datapath gating and patented data-tracking pipeline management technology to reduce power consumption.
The DesignWare minPower Components are tightly integrated with the Synopsys Galaxy Implementation Platform, which enables significant optimization of a design's total power compared to existing flows. The unique architectures in the DesignWare minPower Components allow high-level datapath structures to be automatically optimized based on power costing and switching activities.
Applications with datapath circuits that have a high percentage of active time, such as wireless receivers, audio/video processors, CPUs, media processors, and signal processing blocks for high-performance networking and storage, are ideal candidates for the DesignWare minPower Components.
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