SAN JOSE, USA: Cadence Design Systems Inc. and GLOBALFOUNDRIES Inc., a leading-edge semiconductor manufacturing company, today announced that the two companies have entered into a multi-year software and services agreement for advanced semiconductor design.
As part of the agreement, GLOBALFOUNDRIES has adopted a comprehensive suite of Cadence technologies to aid in the design, verification and manufacturing of complex semiconductor devices targeting process technologies of 45 nanometers and below. In addition, GLOBALFOUNDRIES will team with the Cadence Services organization to build differentiated design-enablement capabilities to support customers at advanced process nodes.
GLOBALFOUNDRIES chose Cadence because of its strong interest in creating a broad, open design flow that enables fast, accurate and easy access to Cadence technology. The foundry has adopted the Cadence Virtuoso and Encounter design environments, as well as specialized technologies for diagnostics, IP validation and parasitic extraction, complemented by support services.
“Cadence technology and services will be important tools to help ensure that GLOBALFOUNDRIES has the enablement infrastructure necessary to support complex customer designs,” said Mojy Chian, senior vice president of design enablement at GLOBALFOUNDRIES.
“Our customers are operating at the leading edge of technology, and it is absolutely critical to offer them a standardized and seamless flow that facilitates working silicon. Cadence’s expertise in custom design is an important addition as we build a global partner ecosystem to efficiently bring the world’s most sophisticated chip designs to market.”
“Providing best-in-class solutions for tomorrow’s toughest design challenges, ahead of the curve, requires continuous innovation and tight collaboration with our customers and business partners,” said Lip-Bu Tan, Cadence president and CEO.
“Working closely with GLOBALFOUNDRIES helps ensure our leadership in low-power, advanced-node, and signoff technologies, and enables Cadence to provide industry-leading design technology and services to a wide range of designers seeking new avenues to market.”
Showing posts with label Cadence Design Systems. Show all posts
Showing posts with label Cadence Design Systems. Show all posts
Tuesday, September 1, 2009
Tuesday, August 25, 2009
EMA's TimingDesigner 9.2 with new interface to Cadence Allegro PCB SI technology
ROCHESTER, USA: EMA Design Automation, one of the world’s largest EDA VARs, recently announced the availability of EMA TimingDesigner 9.2, which interfaces with the Cadence Allegro PCB Signal Integrity (SI) technology providing users with a complete SI and timing design environment.
The TimingDesigner integration with Allegro PCB SI allows customers to do a full signal integrity and timing analysis early in the design phase, with best in class timing reporting technology to quickly and accurately manage timing paths. Engineers can then move their boards to manufacturing with the confidence that the design will operate as expected.
“This new release of TimingDesigner brings our static timing analysis technology into the Cadence signal integrity design flow ensuring correct results while creating an automated, reusable design process,” said Manny Marcano, President and CEO of EMA Design Automation. “This is especially important as timing windows shrink and SI effects increasingly consume timing margins.”
With today’s high speed designs, short timing margins, and tight project schedules, the pressure is on for first pass success. Engineering teams have come to depend on upfront analysis and simulation to provide an early and accurate picture of design behavior when the cost of change is the lowest.
“Merging simulator-derived interconnect delay data into timing tools has previously been a manual and error-prone operation,” said Brad Griffin, Product Marketing Director at Cadence. “With this integrated environment, engineers can now combine the accuracy of simulation with an interactive, comprehensive timing diagram solution to quickly determine if today’s shrinking timing margins are in spec.”
The TimingDesigner graphical interface makes developing and performing analysis on complex timing relationships easy, while enabling review of the entire signal path. Timing can be analyzed across traditional design domains (chip, package, board) allowing timing optimization at the system level.
In addition, TimingDesigner 9.2 includes many new features and enhancements. For ASIC and FPGA design customers, this new version includes enhanced support for SDC generation, 65nm and below support for Altera FPGAs, and a new interface to the Actel Libero development environment.
“Incorporating SI simulated delays into our timing analysis is an absolute must for us,” said Bryn Holmes, Principal Design Engineer - Hardware Engineering, Fujitsu Telecommunications Europe Ltd. “The new TimingDesigner interface allows me to accomplish in 20 minutes what used to take three days. Because of this, I have my entire team using TimingDesigner.”
EMA TimingDesigner 9.2 will be available late August with pricing starting at $2,640 for a 1 year license.
The TimingDesigner integration with Allegro PCB SI allows customers to do a full signal integrity and timing analysis early in the design phase, with best in class timing reporting technology to quickly and accurately manage timing paths. Engineers can then move their boards to manufacturing with the confidence that the design will operate as expected.
“This new release of TimingDesigner brings our static timing analysis technology into the Cadence signal integrity design flow ensuring correct results while creating an automated, reusable design process,” said Manny Marcano, President and CEO of EMA Design Automation. “This is especially important as timing windows shrink and SI effects increasingly consume timing margins.”
With today’s high speed designs, short timing margins, and tight project schedules, the pressure is on for first pass success. Engineering teams have come to depend on upfront analysis and simulation to provide an early and accurate picture of design behavior when the cost of change is the lowest.
“Merging simulator-derived interconnect delay data into timing tools has previously been a manual and error-prone operation,” said Brad Griffin, Product Marketing Director at Cadence. “With this integrated environment, engineers can now combine the accuracy of simulation with an interactive, comprehensive timing diagram solution to quickly determine if today’s shrinking timing margins are in spec.”
The TimingDesigner graphical interface makes developing and performing analysis on complex timing relationships easy, while enabling review of the entire signal path. Timing can be analyzed across traditional design domains (chip, package, board) allowing timing optimization at the system level.
In addition, TimingDesigner 9.2 includes many new features and enhancements. For ASIC and FPGA design customers, this new version includes enhanced support for SDC generation, 65nm and below support for Altera FPGAs, and a new interface to the Actel Libero development environment.
“Incorporating SI simulated delays into our timing analysis is an absolute must for us,” said Bryn Holmes, Principal Design Engineer - Hardware Engineering, Fujitsu Telecommunications Europe Ltd. “The new TimingDesigner interface allows me to accomplish in 20 minutes what used to take three days. Because of this, I have my entire team using TimingDesigner.”
EMA TimingDesigner 9.2 will be available late August with pricing starting at $2,640 for a 1 year license.
Wednesday, August 5, 2009
Nethra enlists Cadence Incisive Palladium accelerator/emulator
SAN JOSE, USA: Cadence Design Systems Inc. announced that Nethra Imaging Inc. reduced the development time of a high-definition (HD) image processor design using the Cadence Incisive Palladium II accelerator/emulator.
Productivity improvements that Nethra experienced with the Palladium product enabled the company to boost design quality and confidence while meeting an ambitious development deadline.
The adoption and rapid deployment of the Palladium II system for the HD image processor ASIC containing more than 25 million gates enabled Nethra’s engineering team to accelerate system-level verification for a leading-edge camera application.
According to Nethra, system-level and subsystem verification was able to achieve 507KHz to 1.3MHz, depending on runtime environments and conditions. With simulation only, verification ran at about 30Hz; accelerated with the Palladium system, Nethra achieved an increase in acceleration 4 orders higher in magnitude at the full chip level.
“The overall productivity gained from Palladium II has dramatically improved our ability to validate our next-generation HD image processor,” said Kasturi Rangam, Nethra’s director of engineering. “The impact of the Palladium II technology was immediate. We went from waiting seven days to process just two HD frames to processing over 120 frames in an hour.”
In addition, the Palladium system’s productivity features, such as runtime checkers, enabled Nethra to pinpoint design issues quickly. Nethra uncovered several artifacts that would have been harder to find without running hundreds of HD frames with system-level stimulus, namely SPI, DDR3, SATA and 10G Ethernet.
The Palladium system’s fast and deterministic compiler, along with the integrated FullVision debugger, were vital for easy bring-up, use and debug.
“We chose the Palladium system for its superior performance, which allowed us to meet our aggressive development schedule and deliver the highest quality HD image processing chip,” said Krishnan Iyer, Nethra’s vice president of engineering. “In addition, the tight support from the Cadence team made the deployment process flawless.”
“Cadence system verification solutions and technologies continue to provide dependability to successful companies such as Nethra,” said Ran Avinun, marketing group director of Cadence system design and verification. “The Palladium system again demonstrated its value through verification acceleration that helped increase productivity, quality and overall confidence.”
Productivity improvements that Nethra experienced with the Palladium product enabled the company to boost design quality and confidence while meeting an ambitious development deadline.
The adoption and rapid deployment of the Palladium II system for the HD image processor ASIC containing more than 25 million gates enabled Nethra’s engineering team to accelerate system-level verification for a leading-edge camera application.
According to Nethra, system-level and subsystem verification was able to achieve 507KHz to 1.3MHz, depending on runtime environments and conditions. With simulation only, verification ran at about 30Hz; accelerated with the Palladium system, Nethra achieved an increase in acceleration 4 orders higher in magnitude at the full chip level.
“The overall productivity gained from Palladium II has dramatically improved our ability to validate our next-generation HD image processor,” said Kasturi Rangam, Nethra’s director of engineering. “The impact of the Palladium II technology was immediate. We went from waiting seven days to process just two HD frames to processing over 120 frames in an hour.”
In addition, the Palladium system’s productivity features, such as runtime checkers, enabled Nethra to pinpoint design issues quickly. Nethra uncovered several artifacts that would have been harder to find without running hundreds of HD frames with system-level stimulus, namely SPI, DDR3, SATA and 10G Ethernet.
The Palladium system’s fast and deterministic compiler, along with the integrated FullVision debugger, were vital for easy bring-up, use and debug.
“We chose the Palladium system for its superior performance, which allowed us to meet our aggressive development schedule and deliver the highest quality HD image processing chip,” said Krishnan Iyer, Nethra’s vice president of engineering. “In addition, the tight support from the Cadence team made the deployment process flawless.”
“Cadence system verification solutions and technologies continue to provide dependability to successful companies such as Nethra,” said Ran Avinun, marketing group director of Cadence system design and verification. “The Palladium system again demonstrated its value through verification acceleration that helped increase productivity, quality and overall confidence.”
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