MUMBAI, INDIA: NVIDIA announced the availability of GRID Test Drive, a simple and secure way to test the power of NVIDIA’s GRID technology for cloud-delivered graphics acceleration from almost any location.
The first of its type, GRID Test Drive is now available in India and is being showcased at VMWare’s vForum – one of India’s largest and most influential virtualization, cloud computing and end-user computing conference.
NVIDIA GRID technology allows knowledge workers and high-end graphics users such as engineers and designers to utilize graphics-rich applications through the cloud anywhere on any device – with the same quality and performance they would have on a professional workstation.
NVIDIA GRID provides a critical performance boost for enterprise users in virtualized environments running anything from basic web-based applications like HTML 5 to professional applications such as PTC Creo, Siemens NX and Dassault Systèmes SOLIDWORKS.
Now, with GRID Test Drive, anyone who is interested in experiencing the benefit of graphics acceleration for virtualized desktops can do so immediately without first having to build a proof-of-concept private cloud. GRID Test Drive accelerates user insight into the benefits of virtualized graphics and provides an easy way for any GRID partner to demonstrate GRID technology.
Friday, October 31, 2014
Synopsys announces DesignWare NVM IP for TowerJazz 180-nm process technology
MOUNTAIN VIEW, USA: Synopsys Inc. announced the availability of the silicon-proven DesignWare AEON Few Time Programmable (FTP) Trim Non-Volatile Memory (NVM) IP for TowerJazz 180-nanometer (nm) SL process technology.
The NVM IP integrates high voltage generation and control circuitry using a standard CMOS technology without the need for additional masks or processing steps. The IP operates from a single core supply, eliminating the complication of providing a separate voltage for NVM programming.
The DesignWare AEON FTP Trim NVM IP provides the smallest area for precision analog IC trimming and sensor calibration applications, in a similar footprint as one-time programmable (OTP) solutions with the advantage of reprogrammability.
"It is critical for us to collaborate with an established IP provider who understands our technology needs and is able to deliver high-quality and feature-rich IP solutions quickly," said Soonwon Hong, VP of Leading Division at TLi. "Integrating Synopsys' proven DesignWare AEON FTP Trim NVM IP for the TowerJazz 180-nanometer process technology delivered the area and performance we required, while reducing integration risk and accelerating our time-to-market by three months."
"Synopsys DesignWare AEON FTP Trim NVM IP enabled us to meet our customers' aggressive schedule requirements and need for small reprogrammable non-volatile memory IP in the TowerJazz 180-nanometer process technology," said Tal Bar (Dotan), director of IP Design Services at TowerJazz. "The combination of Synopsys' trusted IP solution and TowerJazz's IC manufacturing capabilities helps our mutual customers achieve their design goals faster and with less integration risk."
The reprogrammability advantage of the NVM IP enables designers to make in-field calibration updates, which allow end customers to make customizations and changes.
The NVM IP includes necessary support and control circuitry including all high voltage generation and distribution required for programming to reduce system design complexity and IC area. It also supports up to 1 k bit instances, up to 10,000 write cycles, and more than 10 years of data retention at a temperature range (-40 degrees C to +125 degrees C) for industrial applications.
"As a leading provider of reprogrammable NVM IP, Synopsys delivers high-quality solutions that enable designers to incorporate the required functionality into their SoCs with less risk," said John Koeter, VP, marketing for IP and prototyping at Synopsys. "With more than four billion customer ICs shipping with DesignWare NVM IP to-date, Synopsys delivers a silicon-proven, fully qualified NVM IP solution for TowerJazz 180-nanometer process technology that helps designers meet their project schedule and accelerate their time to volume."
The DesignWare AEON Trim NVM IP for TowerJazz 180-nm process is available now. DesignWare NVM IP is also available for multiple other foundries in 250-nm to 40-nm process technologies.
The NVM IP integrates high voltage generation and control circuitry using a standard CMOS technology without the need for additional masks or processing steps. The IP operates from a single core supply, eliminating the complication of providing a separate voltage for NVM programming.
The DesignWare AEON FTP Trim NVM IP provides the smallest area for precision analog IC trimming and sensor calibration applications, in a similar footprint as one-time programmable (OTP) solutions with the advantage of reprogrammability.
"It is critical for us to collaborate with an established IP provider who understands our technology needs and is able to deliver high-quality and feature-rich IP solutions quickly," said Soonwon Hong, VP of Leading Division at TLi. "Integrating Synopsys' proven DesignWare AEON FTP Trim NVM IP for the TowerJazz 180-nanometer process technology delivered the area and performance we required, while reducing integration risk and accelerating our time-to-market by three months."
"Synopsys DesignWare AEON FTP Trim NVM IP enabled us to meet our customers' aggressive schedule requirements and need for small reprogrammable non-volatile memory IP in the TowerJazz 180-nanometer process technology," said Tal Bar (Dotan), director of IP Design Services at TowerJazz. "The combination of Synopsys' trusted IP solution and TowerJazz's IC manufacturing capabilities helps our mutual customers achieve their design goals faster and with less integration risk."
The reprogrammability advantage of the NVM IP enables designers to make in-field calibration updates, which allow end customers to make customizations and changes.
The NVM IP includes necessary support and control circuitry including all high voltage generation and distribution required for programming to reduce system design complexity and IC area. It also supports up to 1 k bit instances, up to 10,000 write cycles, and more than 10 years of data retention at a temperature range (-40 degrees C to +125 degrees C) for industrial applications.
"As a leading provider of reprogrammable NVM IP, Synopsys delivers high-quality solutions that enable designers to incorporate the required functionality into their SoCs with less risk," said John Koeter, VP, marketing for IP and prototyping at Synopsys. "With more than four billion customer ICs shipping with DesignWare NVM IP to-date, Synopsys delivers a silicon-proven, fully qualified NVM IP solution for TowerJazz 180-nanometer process technology that helps designers meet their project schedule and accelerate their time to volume."
The DesignWare AEON Trim NVM IP for TowerJazz 180-nm process is available now. DesignWare NVM IP is also available for multiple other foundries in 250-nm to 40-nm process technologies.
Thursday, October 30, 2014
SEMICON Japan 2014: New venue and new ideas for rebounding industry
TOKYO, JAPAN: SEMI announced an exceptional lineup of speakers for SEMICON Japan’s Opening Day — Accenture, Applied Materials, ARM, IBM Japan, Intel K.K., NIICT, Scripps, Toshiba, and Toyota.
SEMICON Japan 2014, the largest exhibition in Japan for semiconductor manufacturing and related processing technology, will take place at its new venue in Tokyo Big Sight in Tokyo on December 3-5.
A deep program spans from the 33rd annual SEMI Technology Symposium (STS) which begins on December 3, includes sessions on power devices, DFM, lithography, MEMS, packaging, and more to the new World of IoT (Internet of Things).
While the semiconductor and IC manufacturing industries have undergone consolidation, a surge in new investment points to a rebound in related spending in Japan. The semiconductor equipment market in Japan is forecast to grow both in 2014 and 2015.
Drivers for the increased investment are: memory devices, power semiconductors and “More than Moore” semiconductor technologies. According to the SEMI World Fab Forecast, in 2014, Japan will spend more than $10 billion in 2014 on semiconductor equipment and materials. The projection for 2015 is to more than double semiconductor equipment spending to $4.2 billion.
SEMICON Japan 2014 will bring Japan’s rebounding semiconductor equipment market into focus and the underlying technology and business drivers. SEMICON Japan will enable attendees to explore key technologies and business models necessary to grow in the coming years. On December 3, SEMICON Japan opens at 9:30am with a full day of speakers including:
Accenture Japan Ltd — Chikatomo Hodo, president and country managing director.
IBM Japan — Chieko Asakawa, IBM fellow.
Scripps Translational Science Institute — Donald Jones, chief digital officer.
Toyota — Tokuhisa Nomura, executive general manager.
Intel Japan — Makiko Eda, GM and president of Intel Japan.
ARM K.K. — Yuzuru Utsumi, president.
Toshiba — Yasuo Naruke, executive officer, corporate EVP and CEO, semiconductor & storage.
National Institute of Information and Communication Technology (NIICT) — Miwako Doi, auditor.
SEMICON Japan will also highlight emerging opportunities in its workforce composition. In Japan, 14.7 percent of the students in science and engineering departments are women (source: Japan Ministry of Education, Culture, Sports, Science and Technology). SEMI will host a forum on “Women in Business” in Tokyo for the first time to discuss the gender diversity strategy, featuring women executives.
SEMICON Japan 2014, the largest exhibition in Japan for semiconductor manufacturing and related processing technology, will take place at its new venue in Tokyo Big Sight in Tokyo on December 3-5.
A deep program spans from the 33rd annual SEMI Technology Symposium (STS) which begins on December 3, includes sessions on power devices, DFM, lithography, MEMS, packaging, and more to the new World of IoT (Internet of Things).
While the semiconductor and IC manufacturing industries have undergone consolidation, a surge in new investment points to a rebound in related spending in Japan. The semiconductor equipment market in Japan is forecast to grow both in 2014 and 2015.
Drivers for the increased investment are: memory devices, power semiconductors and “More than Moore” semiconductor technologies. According to the SEMI World Fab Forecast, in 2014, Japan will spend more than $10 billion in 2014 on semiconductor equipment and materials. The projection for 2015 is to more than double semiconductor equipment spending to $4.2 billion.
SEMICON Japan 2014 will bring Japan’s rebounding semiconductor equipment market into focus and the underlying technology and business drivers. SEMICON Japan will enable attendees to explore key technologies and business models necessary to grow in the coming years. On December 3, SEMICON Japan opens at 9:30am with a full day of speakers including:
Accenture Japan Ltd — Chikatomo Hodo, president and country managing director.
IBM Japan — Chieko Asakawa, IBM fellow.
Scripps Translational Science Institute — Donald Jones, chief digital officer.
Toyota — Tokuhisa Nomura, executive general manager.
Intel Japan — Makiko Eda, GM and president of Intel Japan.
ARM K.K. — Yuzuru Utsumi, president.
Toshiba — Yasuo Naruke, executive officer, corporate EVP and CEO, semiconductor & storage.
National Institute of Information and Communication Technology (NIICT) — Miwako Doi, auditor.
SEMICON Japan will also highlight emerging opportunities in its workforce composition. In Japan, 14.7 percent of the students in science and engineering departments are women (source: Japan Ministry of Education, Culture, Sports, Science and Technology). SEMI will host a forum on “Women in Business” in Tokyo for the first time to discuss the gender diversity strategy, featuring women executives.
Semiconductor manufacturing: Present at ASMC 2015
SAN JOSE, USA: SEMI announced that the deadline for presenters to submit an abstract for the 26th annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) is extended to November 10.
ASMC, which takes place May 3-6, 2015 in Saratoga Springs, New York, will feature technical presentations of more than 80 peer-reviewed manuscripts covering critical process technologies and fab productivity. This year’s event features keynotes, a panel discussion, networking events, technical sessions on advanced semiconductor manufacturing, and tutorials.
ASMC, in its 26th year, continues to fill a critical need in our industry and provides a venue for industry professionals to network, learn and share knowledge on new and best-method semiconductor manufacturing practices and concepts.
Selected speakers have the opportunity to present in front of IC manufacturers, equipment manufacturers, materials suppliers, chief technology officers, operations managers, process engineers, product managers and academia. Technical abstracts are now due November 10, 2014.
This year, SEMI is including two new technology areas (3D/TSV/Interposer; Fabless Experience). SEMI is soliciting technical abstracts in these key technology areas:
* 3D/TSV/Interposer
* Advanced Metrology
* Advanced Equipment Processes and Materials
* Advanced Patterning / Design for Manufacturability
* Advanced Process Control (APC)
* Contamination Free Manufacturing (CFM)
* Data Management and Data Mining Tools
* Defect Inspection and Reduction
* Discrete Power Devices
* Enabling Technologies and Innovative Devices
* Equipment Reliability and Productivity Enhancements
* Fabless Experience
* Factory Automation
* Green Factory
* Industrial Engineering
* Lean Manufacturing
* Yield Enhancement
* Yield Methodologies.
ASMC, which takes place May 3-6, 2015 in Saratoga Springs, New York, will feature technical presentations of more than 80 peer-reviewed manuscripts covering critical process technologies and fab productivity. This year’s event features keynotes, a panel discussion, networking events, technical sessions on advanced semiconductor manufacturing, and tutorials.
ASMC, in its 26th year, continues to fill a critical need in our industry and provides a venue for industry professionals to network, learn and share knowledge on new and best-method semiconductor manufacturing practices and concepts.
Selected speakers have the opportunity to present in front of IC manufacturers, equipment manufacturers, materials suppliers, chief technology officers, operations managers, process engineers, product managers and academia. Technical abstracts are now due November 10, 2014.
This year, SEMI is including two new technology areas (3D/TSV/Interposer; Fabless Experience). SEMI is soliciting technical abstracts in these key technology areas:
* 3D/TSV/Interposer
* Advanced Metrology
* Advanced Equipment Processes and Materials
* Advanced Patterning / Design for Manufacturability
* Advanced Process Control (APC)
* Contamination Free Manufacturing (CFM)
* Data Management and Data Mining Tools
* Defect Inspection and Reduction
* Discrete Power Devices
* Enabling Technologies and Innovative Devices
* Equipment Reliability and Productivity Enhancements
* Fabless Experience
* Factory Automation
* Green Factory
* Industrial Engineering
* Lean Manufacturing
* Yield Enhancement
* Yield Methodologies.
Wednesday, October 29, 2014
Apple iPad Air 2 largely holds line on features and costs
EL SEGUNDO, USA: With a design and feature set only incrementally different from the original iPad Air, the new iPad Air 2 carries a nearly identical hardware cost as its predecessor, according to the Teardown Analysis Service at IHS Inc.
The 16-gigabyte (GB) Wi-Fi-only version of the Apple iPad Air 2 sports a bill of materials (BOM) of $270, based on a preliminary estimate. When the $5 manufacturing cost is added, the cost rises to $275.
This compares to the $269 BOM for the 16GB version of the original Apple iPad Air, based on a finalized estimate from IHS in November 2013.
Although the profit margin appears to be the same for Apple at the low end of the iPad Air 2 line, the product produces lower gross margins for Apple at the high end with 64GB and 128GB worth of NAND flash. This is because the 64GB and 128GB models of iPad Air 2 are selling at the same price point as the original iPad Air 32GB and 64GB models. The additional cost of memory trims the estimated margins slightly.
“The Air 2 delivers a series of refinements compared to the original Air but features nothing earthshaking,” said Andrew Rassweiler, senior director, cost benchmarking services for IHS.
“With largely identical display specifications and minor improvements in most other areas, Apple continues to offer evolutionary upgrades to the iPad lineup. It’s interesting to note that by offering the consumer a 128GB model for the same price as last year’s 64GB iPad Air, Apple actually has taken down our estimated margins a bit on both the 64GB and 128GB models. The increased memory configurations to 64GB and 128GB are some of the key upgrades here.”
The 16-gigabyte (GB) Wi-Fi-only version of the Apple iPad Air 2 sports a bill of materials (BOM) of $270, based on a preliminary estimate. When the $5 manufacturing cost is added, the cost rises to $275.
This compares to the $269 BOM for the 16GB version of the original Apple iPad Air, based on a finalized estimate from IHS in November 2013.
Although the profit margin appears to be the same for Apple at the low end of the iPad Air 2 line, the product produces lower gross margins for Apple at the high end with 64GB and 128GB worth of NAND flash. This is because the 64GB and 128GB models of iPad Air 2 are selling at the same price point as the original iPad Air 32GB and 64GB models. The additional cost of memory trims the estimated margins slightly.
“The Air 2 delivers a series of refinements compared to the original Air but features nothing earthshaking,” said Andrew Rassweiler, senior director, cost benchmarking services for IHS.
“With largely identical display specifications and minor improvements in most other areas, Apple continues to offer evolutionary upgrades to the iPad lineup. It’s interesting to note that by offering the consumer a 128GB model for the same price as last year’s 64GB iPad Air, Apple actually has taken down our estimated margins a bit on both the 64GB and 128GB models. The increased memory configurations to 64GB and 128GB are some of the key upgrades here.”
SiTime to be acquired by MegaChips for $200 million
SUNNYVALE, USA: SiTime Corp., a MEMS and analog semiconductor company, announced that it has signed a definitive agreement under which MegaChips Corp., a top 25 fabless semiconductor company based in Japan, will acquire SiTime for $200 million in cash.
This transaction combines two complementary fabless semiconductor leaders that provide solutions for the growing Wearables, Mobile and Internet of Things markets.
“SiTime’s founders, Markus Lutz and Dr. Aaron Partridge, started the company with a vision of developing game-changing MEMS and analog technology to revolutionize the $5 billion timing industry,” said Rajesh Vashist, CEO of SiTime.
“Through innovation, passion and focus, we’ve successfully delivered on this vision. Today, SiTime is the overwhelming leader – we have 1000 customers, 250 million units shipped, major design wins in all electronics segments, and a roadmap that extends SiTime’s MEMS technology to all timing markets.”
“Every SiTime employee is excited to be part of MegaChips as we share a common entrepreneurial culture,” continued Vashist. “MegaChips’ financial strength and scale, with SiTime’s innovation and passion, will rapidly accelerate the adoption of MEMS timing solutions.”
While the world of electronics has delivered many innovations, the clock function, which is the heartbeat in all electronics, still uses 75-year-old quartz technology. SiTime’s innovative MEMS timing solutions replace dated quartz products in the telecom, networking, computing, storage and consumer markets, with the benefits of higher performance, smaller size, and lower power and cost.
This transaction combines two complementary fabless semiconductor leaders that provide solutions for the growing Wearables, Mobile and Internet of Things markets.
“SiTime’s founders, Markus Lutz and Dr. Aaron Partridge, started the company with a vision of developing game-changing MEMS and analog technology to revolutionize the $5 billion timing industry,” said Rajesh Vashist, CEO of SiTime.
“Through innovation, passion and focus, we’ve successfully delivered on this vision. Today, SiTime is the overwhelming leader – we have 1000 customers, 250 million units shipped, major design wins in all electronics segments, and a roadmap that extends SiTime’s MEMS technology to all timing markets.”
“Every SiTime employee is excited to be part of MegaChips as we share a common entrepreneurial culture,” continued Vashist. “MegaChips’ financial strength and scale, with SiTime’s innovation and passion, will rapidly accelerate the adoption of MEMS timing solutions.”
While the world of electronics has delivered many innovations, the clock function, which is the heartbeat in all electronics, still uses 75-year-old quartz technology. SiTime’s innovative MEMS timing solutions replace dated quartz products in the telecom, networking, computing, storage and consumer markets, with the benefits of higher performance, smaller size, and lower power and cost.
Tuesday, October 28, 2014
Mentor Graphics announces Xpedition system designer for comprehensive multi-board systems development
WILSONVILLE, USA: Mentor Graphics Corp. announced its newest offering and key building block in the Xpedition® platform, the Xpedition Systems Designer product for multi-board systems connectivity.
The Xpedition Systems Designer product captures the hardware description of multi-board systems, from logical system definition down to the individual PCBs, automating multi-level system design synchronization processes to ensure team collaboration with accuracy and faster design productivity.
Current systems design processes for advanced electronics are fraught with multiple, disconnected tools used for system definition, with no standard methodology to synchronize and transfer design data between design disciplines and abstraction levels. This results in incorrect electrical connections, mechanical interference, and the high costs of manual synchronization.
The Xpedition Systems Designer product resolves this problem as the industry's only single, integrated, and automated methodology that captures complete logic system definitions. The system may consist of multiple boards, cables and other system elements, such as backplane, cable assemblies, sensors and actuators. This solution enables consistency and completeness of the multi-board system description.
"Systems design involves collaboration across disciplines, and is critical to modern product development. Traditional design practices isolate systems capture from the rest of the process, lowering team productivity, stifling innovation, and increasing product cost," stated John MacKrell, VP, Systems Engineering Knowledge Council lead of CIMdata. "Mentor Graphics' new systems design technology enables engineering teams to capture system designs, while collaborating effectively with all those involved in the design and implementation process to optimize the end product."
The Xpedition Systems Designer product replaces time- and resource-consuming manual processes and the redundant re-entry of data with automatic synchronization of design changes across multiple levels and disciplines.
This unique design "cockpit" enables system-wide partitioning of logical system blocks into individual PCBs. The environment fully supports concurrent design, enabling team members to simultaneously engineer and collaborate on different components of the system.
"Our new Xpedition platform delivers 'industry-first' technologies and our new Systems Designer product is a clear example," stated Henry Potts, VP and GM of Mentor Graphics Systems Design Division. "Xpedition Systems Designer was developed as the industry's best environment for design connectivity and team collaboration to deliver consistency of design integrity across disparate domains, tools and individuals."
The Xpedition Systems Designer product captures the hardware description of multi-board systems, from logical system definition down to the individual PCBs, automating multi-level system design synchronization processes to ensure team collaboration with accuracy and faster design productivity.
Current systems design processes for advanced electronics are fraught with multiple, disconnected tools used for system definition, with no standard methodology to synchronize and transfer design data between design disciplines and abstraction levels. This results in incorrect electrical connections, mechanical interference, and the high costs of manual synchronization.
The Xpedition Systems Designer product resolves this problem as the industry's only single, integrated, and automated methodology that captures complete logic system definitions. The system may consist of multiple boards, cables and other system elements, such as backplane, cable assemblies, sensors and actuators. This solution enables consistency and completeness of the multi-board system description.
"Systems design involves collaboration across disciplines, and is critical to modern product development. Traditional design practices isolate systems capture from the rest of the process, lowering team productivity, stifling innovation, and increasing product cost," stated John MacKrell, VP, Systems Engineering Knowledge Council lead of CIMdata. "Mentor Graphics' new systems design technology enables engineering teams to capture system designs, while collaborating effectively with all those involved in the design and implementation process to optimize the end product."
The Xpedition Systems Designer product replaces time- and resource-consuming manual processes and the redundant re-entry of data with automatic synchronization of design changes across multiple levels and disciplines.
This unique design "cockpit" enables system-wide partitioning of logical system blocks into individual PCBs. The environment fully supports concurrent design, enabling team members to simultaneously engineer and collaborate on different components of the system.
"Our new Xpedition platform delivers 'industry-first' technologies and our new Systems Designer product is a clear example," stated Henry Potts, VP and GM of Mentor Graphics Systems Design Division. "Xpedition Systems Designer was developed as the industry's best environment for design connectivity and team collaboration to deliver consistency of design integrity across disparate domains, tools and individuals."
Synopsys' USB 3.1 IP solution enables 10 Gbps data transfer speeds
MOUNTAIN VIEW, USA: Synopsys Inc. has introduced the industry's first USB 3.1 IP solution, consisting of DesignWare USB 3.1 Device Controller, an IP Virtual Development Kit (VDK) and verification IP (VIP) to accelerate the development of high-performance storage, digital office and mobile system-on-chip (SoC) applications.
Synopsys' DesignWare USB 3.1 IP solutions support 10 Gbps data transfer rates, power-down capabilities and compatibility with existing USB 3.0 software stacks and device protocols. Based on the DesignWare USB 3.0 Controller IP architecture, which has shipped in more than 100 million SoCs, the DesignWare USB 3.1 Device Controller IP enables designers to integrate USB 3.1 functionality with significantly less risk and faster time-to-market.
"Mobile, storage and digital office applications that will take advantage of USB 3.1's 10 Gbps performance are in development now," said Terry Moore, CEO at MCCI. "Designers facing tight schedules can save up to twenty months of engineering effort by using their existing DesignWare USB 3.0 software or, if changing controllers or operating systems, by using MCCI's pre-tested off-the-shelf Datapump USB device stack."
"As an active member of the USB-IF for more than 18 years, Synopsys continues to develop IP products that ease the integration and adoption of the latest USB specifications," said Jeff Ravencraft, USB-IF president and COO. "Initial USB 3.1 products are expected to appear in early 2015 and the availability of integration-ready USB 3.1 IP is critical. Companies like Synopsys give designers the ability to more easily incorporate the USB 3.1 interface into their SoCs, pushing USB performance ever higher."
The DesignWare USB 3.1 IP VDK, part of the Synopsys IP Accelerated initiative, helps developers quickly bring-up, enhance and optimize existing software for their specific DesignWare USB 3.1 Device Controller configuration.
The IP VDK consists of a reference virtual prototype that includes a processor subsystem reference design, a configurable model of the DesignWare USB 3.1 Controller IP, a Linux software stack and reference drivers.
Software developers can use the IP VDK as a proven target for early software development, bring-up, debug and test in parallel with SoC development. Hardware developers can use the HAPS® FPGA-based prototyping system for hardware/software integration and system validation of USB 3.1 designs, as demonstrated in November 2013.
Synopsys' USB 3.1 VIP is based on Synopsys' native SystemVerilog and native UVM architecture, offering ease of integration, high performance, configurability, coverage and debug to speed the protocol verification process.
The USB 3.1 VIP supports Verdi Protocol Analyzer, a protocol-centric debug environment that substantially increases user productivity with protocol-aware features to simplify viewing and debug of complex protocols.
"As a leading provider of USB IP for more than a decade, Synopsys provides the high-quality IP designers need to meet their evolving power, performance and area requirements," said John Koeter, VP of marketing for IP and prototyping at Synopsys. "With our extensive knowledge in developing USB IP, more than 3,000 USB design wins and billions of SoCs shipped with DesignWare USB IP, designers know they can rely on Synopsys when integrating the latest USB functionality into their SoCs."
Synopsys' DesignWare USB 3.1 IP solutions support 10 Gbps data transfer rates, power-down capabilities and compatibility with existing USB 3.0 software stacks and device protocols. Based on the DesignWare USB 3.0 Controller IP architecture, which has shipped in more than 100 million SoCs, the DesignWare USB 3.1 Device Controller IP enables designers to integrate USB 3.1 functionality with significantly less risk and faster time-to-market.
"Mobile, storage and digital office applications that will take advantage of USB 3.1's 10 Gbps performance are in development now," said Terry Moore, CEO at MCCI. "Designers facing tight schedules can save up to twenty months of engineering effort by using their existing DesignWare USB 3.0 software or, if changing controllers or operating systems, by using MCCI's pre-tested off-the-shelf Datapump USB device stack."
"As an active member of the USB-IF for more than 18 years, Synopsys continues to develop IP products that ease the integration and adoption of the latest USB specifications," said Jeff Ravencraft, USB-IF president and COO. "Initial USB 3.1 products are expected to appear in early 2015 and the availability of integration-ready USB 3.1 IP is critical. Companies like Synopsys give designers the ability to more easily incorporate the USB 3.1 interface into their SoCs, pushing USB performance ever higher."
The DesignWare USB 3.1 IP VDK, part of the Synopsys IP Accelerated initiative, helps developers quickly bring-up, enhance and optimize existing software for their specific DesignWare USB 3.1 Device Controller configuration.
The IP VDK consists of a reference virtual prototype that includes a processor subsystem reference design, a configurable model of the DesignWare USB 3.1 Controller IP, a Linux software stack and reference drivers.
Software developers can use the IP VDK as a proven target for early software development, bring-up, debug and test in parallel with SoC development. Hardware developers can use the HAPS® FPGA-based prototyping system for hardware/software integration and system validation of USB 3.1 designs, as demonstrated in November 2013.
Synopsys' USB 3.1 VIP is based on Synopsys' native SystemVerilog and native UVM architecture, offering ease of integration, high performance, configurability, coverage and debug to speed the protocol verification process.
The USB 3.1 VIP supports Verdi Protocol Analyzer, a protocol-centric debug environment that substantially increases user productivity with protocol-aware features to simplify viewing and debug of complex protocols.
"As a leading provider of USB IP for more than a decade, Synopsys provides the high-quality IP designers need to meet their evolving power, performance and area requirements," said John Koeter, VP of marketing for IP and prototyping at Synopsys. "With our extensive knowledge in developing USB IP, more than 3,000 USB design wins and billions of SoCs shipped with DesignWare USB IP, designers know they can rely on Synopsys when integrating the latest USB functionality into their SoCs."
Synopsys IC Compiler II delivers five-fold implementation speed up
MOUNTAIN VIEW, USA: Synopsys Inc. announced that its IC Complier II place-and-route tool enabled Panasonic Corporation System LSI Business Division (Panasonic SoC) to achieve silicon success with their high-end multimedia chip.
Unveiled at Synopsys User Group (SNUG) in Silicon Valley earlier this year, IC Compiler II is a game-changing successor to the IC Compiler product, the industry's current leading place-and-route solution for advanced designs at both established and emerging nodes.
Key capabilities in IC Compiler II include rapid design exploration, unique new clock-building, analytics-driven optimization to boost quality-of-results and extensive use of multi-mode and multi-corner optimization throughout the flow to accelerate turnaround time. The unique benefits it offered with five times faster implementation, IC Compiler II is now seeing expanded use to other designs at 40 nanometer (nm) and 28 nm process technology nodes.
"IC Compiler II was instrumental in enabling us to hit our market window and achieve silicon success for our complex multimedia chip. We are now entering volume production," said Hiroki Tomoshige, GM at Panasonic Corp. System LSI Business Division, Division 3, Second Development Group. "We are very pleased with the breakthrough performance IC Compiler II has delivered to shorten our design cycles and get our competitive products to market faster."
IC Compiler II was built from the ground up to deliver a major leap forward in physical design productivity. Based on a new multi-everything infrastructure and multicore technology that enables ultra-high-capacity design planning capability, unique clocking technology and advanced global and analytical closure techniques, IC Compiler II delivers a groundbreaking 10-times increase in design throughput.
IC Complier II's "analytically-global" optimization provides faster, broader and more convergent physical synthesis and closure. This natively multi-threaded technique utilizes new, highly scalable timing and extraction engines that enable extensive multi-corner and multi-mode (MCMM) optimization. Early and broad analysis enables optimization for large number of concurrent scenarios, improving signoff convergence and reducing ECO iterations to a minimum.
Additionally, patent-pending MCMM-aware local-skew clock construction techniques enable significant speed up in the building of complex clock networks with hundreds of domains and achieve the high-frequency clock requirements that are typical for the success of high-end chips.
"The unique benefits it offers with five times faster implementation illustrates why our customers are seeing IC Compiler II as a game-changing solution that is redefining the implementation landscape," said Antun Domic, executive VP and GM of the Design Group at Synopsys. "We are engaged broadly to bring the power of 10X delivered by IC Compiler II to more customers and help them get more competitive products to market faster."
Unveiled at Synopsys User Group (SNUG) in Silicon Valley earlier this year, IC Compiler II is a game-changing successor to the IC Compiler product, the industry's current leading place-and-route solution for advanced designs at both established and emerging nodes.
Key capabilities in IC Compiler II include rapid design exploration, unique new clock-building, analytics-driven optimization to boost quality-of-results and extensive use of multi-mode and multi-corner optimization throughout the flow to accelerate turnaround time. The unique benefits it offered with five times faster implementation, IC Compiler II is now seeing expanded use to other designs at 40 nanometer (nm) and 28 nm process technology nodes.
"IC Compiler II was instrumental in enabling us to hit our market window and achieve silicon success for our complex multimedia chip. We are now entering volume production," said Hiroki Tomoshige, GM at Panasonic Corp. System LSI Business Division, Division 3, Second Development Group. "We are very pleased with the breakthrough performance IC Compiler II has delivered to shorten our design cycles and get our competitive products to market faster."
IC Compiler II was built from the ground up to deliver a major leap forward in physical design productivity. Based on a new multi-everything infrastructure and multicore technology that enables ultra-high-capacity design planning capability, unique clocking technology and advanced global and analytical closure techniques, IC Compiler II delivers a groundbreaking 10-times increase in design throughput.
IC Complier II's "analytically-global" optimization provides faster, broader and more convergent physical synthesis and closure. This natively multi-threaded technique utilizes new, highly scalable timing and extraction engines that enable extensive multi-corner and multi-mode (MCMM) optimization. Early and broad analysis enables optimization for large number of concurrent scenarios, improving signoff convergence and reducing ECO iterations to a minimum.
Additionally, patent-pending MCMM-aware local-skew clock construction techniques enable significant speed up in the building of complex clock networks with hundreds of domains and achieve the high-frequency clock requirements that are typical for the success of high-end chips.
"The unique benefits it offers with five times faster implementation illustrates why our customers are seeing IC Compiler II as a game-changing solution that is redefining the implementation landscape," said Antun Domic, executive VP and GM of the Design Group at Synopsys. "We are engaged broadly to bring the power of 10X delivered by IC Compiler II to more customers and help them get more competitive products to market faster."
Micron, Wave Systems, Lenovo and American Megatrends to create new industry standard to meet global security requirements
BOISE, USA: Micron Technology Inc.and Wave Systems Corp. intend to expand their collaboration to include Lenovo and American Megatrends Inc.(AMI).
The four companies plan to develop advanced enterprise-class security offerings to address the escalating concerns of governments and multinational businesses.
To meet the overall objective of verifying and securing software components, these solutions will significantly strengthen the Core Root of Trust for Measurement (CRTM) to offer best-in-class protection against current and emerging pre-boot threats within the supply chain. The companies intend for these solutions to form the basis of a new industry standard designed to ensure the integrity of the supply chain.
According to the 2014 Verizon DBIR report, supply chain vulnerabilities and third-party vendors are still a leading cause of enterprise data breaches (Source, Verizon DBIR, 2014). With major brands continually leaking sensitive enterprise data, it is becoming even more critical to architect a comprehensive enterprise security suite that protects memory content from its inception in manufacturing throughout a computing device's life cycle.
By providing verification of the CRTM, the first BIOS code that executes, the security of system measurements can be ensured rather than implicitly trusted, reducing the risk of supply chain attacks. A centrally managed security solution working in conjunction with a client's core root of trust for measurement provides client system integrity throughout the supply chain.
A combined security solution from Micron, Wave, Lenovo and AMI would address the foundational level of a client's security by enabling advanced protection, detection and recovery capabilities for memory content, creating an unrivaled level of trust from the supply chain to the corporate environment. The planned software solution will integrate with the Trusted Platform Module and other hardware components to provide notification, remote management, and further remediation options for the enterprise.
The four companies plan to develop advanced enterprise-class security offerings to address the escalating concerns of governments and multinational businesses.
To meet the overall objective of verifying and securing software components, these solutions will significantly strengthen the Core Root of Trust for Measurement (CRTM) to offer best-in-class protection against current and emerging pre-boot threats within the supply chain. The companies intend for these solutions to form the basis of a new industry standard designed to ensure the integrity of the supply chain.
According to the 2014 Verizon DBIR report, supply chain vulnerabilities and third-party vendors are still a leading cause of enterprise data breaches (Source, Verizon DBIR, 2014). With major brands continually leaking sensitive enterprise data, it is becoming even more critical to architect a comprehensive enterprise security suite that protects memory content from its inception in manufacturing throughout a computing device's life cycle.
By providing verification of the CRTM, the first BIOS code that executes, the security of system measurements can be ensured rather than implicitly trusted, reducing the risk of supply chain attacks. A centrally managed security solution working in conjunction with a client's core root of trust for measurement provides client system integrity throughout the supply chain.
A combined security solution from Micron, Wave, Lenovo and AMI would address the foundational level of a client's security by enabling advanced protection, detection and recovery capabilities for memory content, creating an unrivaled level of trust from the supply chain to the corporate environment. The planned software solution will integrate with the Trusted Platform Module and other hardware components to provide notification, remote management, and further remediation options for the enterprise.
eInfochips demos medical imaging, video processing and mechanical engineering solutions for medical devices
AHMEDABAD, INDIA: eInfochips, a leading engineering R&D services company, will be at MedTech World’s popular MD&M event in Minneapolis to demonstrate its software, mechanical and hardware engineering services available for design of IEC 60601, IEC 62304 and ISO14971 compliant medical devices.
The company will highlight its track record of improving time-to-market for Fortune 500 clients on medical imaging, diagnostics, tele-medicine, wearable medical devices, and surgical equipment.
Parag Mehta, chief marketing and business development officer at eInfochips, said: “We see a transformation in the industry, with products becoming power-efficient, performance-driven that come with ultra-small form factors. We are leading this transition with our design, test and re-engineering services for Fortune 500 companies.”
The company will showcase its expertise at MD&M Minneapolis Conference at Booth #1052, on 29th & 30th Oct 2014
The company will highlight its track record of improving time-to-market for Fortune 500 clients on medical imaging, diagnostics, tele-medicine, wearable medical devices, and surgical equipment.
Parag Mehta, chief marketing and business development officer at eInfochips, said: “We see a transformation in the industry, with products becoming power-efficient, performance-driven that come with ultra-small form factors. We are leading this transition with our design, test and re-engineering services for Fortune 500 companies.”
The company will showcase its expertise at MD&M Minneapolis Conference at Booth #1052, on 29th & 30th Oct 2014
Symtavision and Renesas collaborate on joint timing analysis methodology for multicore MCUs
BRAUNSCHWEIG, GERMANY: Closely collaborating with Renesas Electronics, Symtavision, the global leader in timing analysis solutions for planning, optimizing and verifying embedded real-time systems, has developed an integrated, model- and trace-based methodology for the Renesas RH850 family of multicore MCUs as well as other Renesas target MCU architectures.
Central to the Symtavision/Renesas integrated methodology for multicore ECUs are Symtavision’s SymTA/S tool suite for model-based timing analysis, optimization and synthesis, combined with Symtavision’s powerful TraceAnalyzer solution for visualizing and analyzing timing from measurements and simulations.
Both SymTA/S and TraceAnalyzer are used extensively in the automotive industry for developing efficient, safe and reliable ECUs, networks and distributed systems.
The methodology involves target tracing to gather fundamental timing data in a realistic environment on the target platform (or one that is predictably related). A range of established tracing tools such as those from Green Hills Software, Gliwa, iSYSTEM or Lauterbach can be used for this purpose.
Symtavision’s TraceAnalyzer then processes this data to visualize and validate the internal scheduling of the device and derive key metrics such as memory access times, runnable execution times and patterns of sporadic interrupts. This allows the simple creation of dedicated RH850 virtual performance models in SymTA/S.
These models facilitate an early assessment of design alternatives to ensure that all software can execute in real-time and also provide a basis for the continuous validation of model assumptions versus actual implementation.
Furthermore, the dedicated RH850 models ensure that key multicore-related design challenges such as optimal software and task partitioning, as well as data allocation and arbitration, are systematically addressed. The models can be extended seamlessly to analysis of distributed functions over CAN, Ethernet, FlexRay or LIN.
Central to the Symtavision/Renesas integrated methodology for multicore ECUs are Symtavision’s SymTA/S tool suite for model-based timing analysis, optimization and synthesis, combined with Symtavision’s powerful TraceAnalyzer solution for visualizing and analyzing timing from measurements and simulations.
Both SymTA/S and TraceAnalyzer are used extensively in the automotive industry for developing efficient, safe and reliable ECUs, networks and distributed systems.
The methodology involves target tracing to gather fundamental timing data in a realistic environment on the target platform (or one that is predictably related). A range of established tracing tools such as those from Green Hills Software, Gliwa, iSYSTEM or Lauterbach can be used for this purpose.
Symtavision’s TraceAnalyzer then processes this data to visualize and validate the internal scheduling of the device and derive key metrics such as memory access times, runnable execution times and patterns of sporadic interrupts. This allows the simple creation of dedicated RH850 virtual performance models in SymTA/S.
These models facilitate an early assessment of design alternatives to ensure that all software can execute in real-time and also provide a basis for the continuous validation of model assumptions versus actual implementation.
Furthermore, the dedicated RH850 models ensure that key multicore-related design challenges such as optimal software and task partitioning, as well as data allocation and arbitration, are systematically addressed. The models can be extended seamlessly to analysis of distributed functions over CAN, Ethernet, FlexRay or LIN.
Automotive bus technology delivers superior digital audio quality
USA: Analog Devices Inc. has introduced a digital audio bus technology capable of distributing audio and control data together with clock and power over a single, unshielded twisted-pair wire.
The AD2410 transceiver is the first in a family of devices that enables ADI’s new Automotive Audio Bus (A²B), which significantly reduces the weight of existing cable harnesses, resulting in improved vehicle fuel efficiency while delivering high fidelity audio. The AD2410 transceiver also eliminates the need for expensive microcontrollers with large memories that are required in existing digital bus architectures.
“As an early implementer of ADI’s A²B, Panasonic Automotive found the technology to significantly reduce cabling complexity and associated cost and weight of next-generation infotainment systems, key areas of focus for Panasonic’s OEM customers,” said Jonathan Lane, Group manager, Audio & Acoustics, part of Panasonic Automotive Systems Co. of America (PASA) Advanced Development Engineering.
“We believe A²B to be well suited to address applications such as microphone arrays and Active Noise Cancellation, a leading area of expertise for Panasonic that we expect to be an integral component of next-generation infotainment systems.”
The AD2410 transceiver is the first in a family of devices that enables ADI’s new Automotive Audio Bus (A²B), which significantly reduces the weight of existing cable harnesses, resulting in improved vehicle fuel efficiency while delivering high fidelity audio. The AD2410 transceiver also eliminates the need for expensive microcontrollers with large memories that are required in existing digital bus architectures.
“As an early implementer of ADI’s A²B, Panasonic Automotive found the technology to significantly reduce cabling complexity and associated cost and weight of next-generation infotainment systems, key areas of focus for Panasonic’s OEM customers,” said Jonathan Lane, Group manager, Audio & Acoustics, part of Panasonic Automotive Systems Co. of America (PASA) Advanced Development Engineering.
“We believe A²B to be well suited to address applications such as microphone arrays and Active Noise Cancellation, a leading area of expertise for Panasonic that we expect to be an integral component of next-generation infotainment systems.”
Cadence announces Virtuoso Liberate AMS
SAN JOSE, USA: Cadence Design Systems Inc. announced the Cadence Virtuoso Liberate AMS characterization solution, the industry's first dynamic simulation characterization solution for mixed-signal blocks such as phase-locked loops (PLLs), data converters, high-speed transceivers and I/Os.
Built upon the proven Cadence Liberate characterization platform, Virtuoso Liberate AMS characterizes post-layout netlists of mixed-signal macros with millions of associated parasitic elements 20X faster than traditional "divide and conquer" FastSPICE simulation methods and with true SPICE accuracy to enable accurate system-on-chip (SoC) signoff.
With the increasing complexity of SoCs, and the industry shift towards intellectual property (IP) reuse and digital-on-top design flows for signoff with static analysis tools, Liberty representations are required for all blocks in the design including mixed-signal macros.
To simplify this process, Virtuoso Liberate AMS automates standard Liberty model creation for large mixed-signal macro blocks by capturing the interaction between digital and analog paths and modeling it into a final Liberty library.
To increase throughput and reduce turnaround time from weeks to hours, Virtuoso Liberate AMS integrates Cadence's advanced FastSPICE technology, Spectre® XPS, and employs a unique hybrid partitioning approach to statically identify required arcs and dynamically exercise them to characterize large mixed-signal blocks.
This hybrid partitioning approach identifies circuit activity at the block level to carve out a critical-path partition for each logic arc and then characterizes each partition with true SPICE accuracy to create highly accurate library models.
For custom circuit designers, Virtuoso Liberate AMS is integrated with Virtuoso Analog Design Environment XL and leverages Virtuoso Analog Design Environment XL testbenches and setup to quickly move from circuit design validation into library generation.
"Prior to using Virtuoso Liberate AMS, the characterization process for mixed-signal blocks was an error-prone manual process," said Darren Engelkemier, VP of Digital IC Engineering, of Aquantia Corp. "With Virtuoso Liberate AMS, our design teams were able to automate this task by eliminating netlist processing and getting more accurate and reliable data especially for our custom cells with non-standard structures at circuit-level."
"Cadence is committed to providing its customers with world-class simulation and characterization solutions," said Tom Beckley, senior VP, Custom IC and PCB Group at Cadence. "Virtuoso Liberate AMS extends the company's leadership in mixed-signal flows, and gives designers a powerful new solution to increase their productivity and reduce their time to market."
Built upon the proven Cadence Liberate characterization platform, Virtuoso Liberate AMS characterizes post-layout netlists of mixed-signal macros with millions of associated parasitic elements 20X faster than traditional "divide and conquer" FastSPICE simulation methods and with true SPICE accuracy to enable accurate system-on-chip (SoC) signoff.
With the increasing complexity of SoCs, and the industry shift towards intellectual property (IP) reuse and digital-on-top design flows for signoff with static analysis tools, Liberty representations are required for all blocks in the design including mixed-signal macros.
To simplify this process, Virtuoso Liberate AMS automates standard Liberty model creation for large mixed-signal macro blocks by capturing the interaction between digital and analog paths and modeling it into a final Liberty library.
To increase throughput and reduce turnaround time from weeks to hours, Virtuoso Liberate AMS integrates Cadence's advanced FastSPICE technology, Spectre® XPS, and employs a unique hybrid partitioning approach to statically identify required arcs and dynamically exercise them to characterize large mixed-signal blocks.
This hybrid partitioning approach identifies circuit activity at the block level to carve out a critical-path partition for each logic arc and then characterizes each partition with true SPICE accuracy to create highly accurate library models.
For custom circuit designers, Virtuoso Liberate AMS is integrated with Virtuoso Analog Design Environment XL and leverages Virtuoso Analog Design Environment XL testbenches and setup to quickly move from circuit design validation into library generation.
"Prior to using Virtuoso Liberate AMS, the characterization process for mixed-signal blocks was an error-prone manual process," said Darren Engelkemier, VP of Digital IC Engineering, of Aquantia Corp. "With Virtuoso Liberate AMS, our design teams were able to automate this task by eliminating netlist processing and getting more accurate and reliable data especially for our custom cells with non-standard structures at circuit-level."
"Cadence is committed to providing its customers with world-class simulation and characterization solutions," said Tom Beckley, senior VP, Custom IC and PCB Group at Cadence. "Virtuoso Liberate AMS extends the company's leadership in mixed-signal flows, and gives designers a powerful new solution to increase their productivity and reduce their time to market."
Monday, October 27, 2014
Cadence announces industry's first 25G Ethernet verification IP
SAN JOSE, USA: Cadence Design Systems Inc. announced the industry's first Verification IP (VIP) supporting the new 25-Gigabit (25G) Ethernet specification.
The 25G Ethernet specification extends the IEEE 802.3 standard to include operation at 25 Gb/s over copper cables and backplanes and increases server network throughput without using more interconnect lanes. Cadence 25G Ethernet VIP offers full verification support for both MAC and PHY designs while providing greater assurance that the design can operate as expected.
This new 25G Ethernet specification was created by the 25G Ethernet Consortium, with the goal of supporting an industry-standard, interoperable Ethernet specification that boosts performance and slashes interconnect cost. Cadence VIP also supports the 50G definition included in 25G Ethernet, which offers 2X port reduction and a 25 percent bandwidth improvement compared to 40G.
"The new 25G Ethernet specification and 50G definition enables the cost-efficient scaling of network bandwidth delivered to server and storage endpoints in next-generation cloud infrastructure," said Brad Booth, secretary, 25G Ethernet Consortium. "As one of the Consortium's early members, Cadence is enabling further adoption of the 25G Ethernet specification and 50G definition through the delivery of verification IP."
"25G Ethernet is an important new technology that is satisfying the ever-increasing need for scale in the datacenter in a cost-effective manner," said Martin Lund, senior VP of the IP Group at Cadence. "We continue to invest in VIP that accelerates industry adoption of new interface technology. Being first to market with VIP enables our customers to be first to market with their next-generation products."
The 25G Ethernet specification extends the IEEE 802.3 standard to include operation at 25 Gb/s over copper cables and backplanes and increases server network throughput without using more interconnect lanes. Cadence 25G Ethernet VIP offers full verification support for both MAC and PHY designs while providing greater assurance that the design can operate as expected.
This new 25G Ethernet specification was created by the 25G Ethernet Consortium, with the goal of supporting an industry-standard, interoperable Ethernet specification that boosts performance and slashes interconnect cost. Cadence VIP also supports the 50G definition included in 25G Ethernet, which offers 2X port reduction and a 25 percent bandwidth improvement compared to 40G.
"The new 25G Ethernet specification and 50G definition enables the cost-efficient scaling of network bandwidth delivered to server and storage endpoints in next-generation cloud infrastructure," said Brad Booth, secretary, 25G Ethernet Consortium. "As one of the Consortium's early members, Cadence is enabling further adoption of the 25G Ethernet specification and 50G definition through the delivery of verification IP."
"25G Ethernet is an important new technology that is satisfying the ever-increasing need for scale in the datacenter in a cost-effective manner," said Martin Lund, senior VP of the IP Group at Cadence. "We continue to invest in VIP that accelerates industry adoption of new interface technology. Being first to market with VIP enables our customers to be first to market with their next-generation products."
SMIC and ASML sign volume purchase agreement worth 450 million Euros
SHANGHAI, CHINA: Semiconductor Manufacturing International Corp. and ASML Holding N.V. announced the signing of a volume purchase agreement (VPA) that will provide SMIC with lithography systems from ASML.
The VPA which is worth approximately 450 million Euros and is part of a strategic partnership between the companies that will help facilitate the timely expansion of SMIC's advanced technology capacities.
Lithography is a critical step in the manufacturing of semiconductors and helps to create complex structures that make up the transistors on a wafer.
Under the agreement ASML will provide lithography tools such as the TWINSCAN NXT system designed for volume production of 300mm wafers at the 32nm node and beyond. Some of the specific benefits include increased productivity, unprecedented overlay performance and maximum image performance for each wafer.
"SMIC is the most advanced wafer foundry in China and ASML is the leading provider for lithography systems, and we believe that this partnership will complement both sides" said Dr. Tzu-Yin Chiu, CEO and executive director of SMIC. "We chose ASML as our provider due to their world-class products and services, and this cooperation will facilitate and strengthen the development of our advanced technologies."
"ASML is always committed to provide services that match the needs of our customers," said Peter Wennink, president and CEO of ASML.
"We are pleased to have SMIC as one of our customers, and the purchase of our lithography systems shows SMIC's recognition and trust in our technology. China is an important market for us and through this agreement, we hope to increase our presence and gain a stronger foothold with the Chinese customers. We believe this is a win-win solution where both parties can benefit from the deal."
Lilianne Ploumen, the Dutch Minister for Foreign Trade and Development Cooperation, accompanied by members of the Dutch Consulate, attended the signing ceremony as part of an economic mission to strengthen economic ties between the Netherlands and China.
At the ceremony, Minister Ploumen said: "China is an important market that continues to grow. The signing ceremony between SMIC and ASML marks the increasing high-tech cooperation between China and the Netherlands, and I sincerely hope that this continues to develop further."
The VPA which is worth approximately 450 million Euros and is part of a strategic partnership between the companies that will help facilitate the timely expansion of SMIC's advanced technology capacities.
Lithography is a critical step in the manufacturing of semiconductors and helps to create complex structures that make up the transistors on a wafer.
Under the agreement ASML will provide lithography tools such as the TWINSCAN NXT system designed for volume production of 300mm wafers at the 32nm node and beyond. Some of the specific benefits include increased productivity, unprecedented overlay performance and maximum image performance for each wafer.
"SMIC is the most advanced wafer foundry in China and ASML is the leading provider for lithography systems, and we believe that this partnership will complement both sides" said Dr. Tzu-Yin Chiu, CEO and executive director of SMIC. "We chose ASML as our provider due to their world-class products and services, and this cooperation will facilitate and strengthen the development of our advanced technologies."
"ASML is always committed to provide services that match the needs of our customers," said Peter Wennink, president and CEO of ASML.
"We are pleased to have SMIC as one of our customers, and the purchase of our lithography systems shows SMIC's recognition and trust in our technology. China is an important market for us and through this agreement, we hope to increase our presence and gain a stronger foothold with the Chinese customers. We believe this is a win-win solution where both parties can benefit from the deal."
Lilianne Ploumen, the Dutch Minister for Foreign Trade and Development Cooperation, accompanied by members of the Dutch Consulate, attended the signing ceremony as part of an economic mission to strengthen economic ties between the Netherlands and China.
At the ceremony, Minister Ploumen said: "China is an important market that continues to grow. The signing ceremony between SMIC and ASML marks the increasing high-tech cooperation between China and the Netherlands, and I sincerely hope that this continues to develop further."
SK Hynix accelerates memory development with Synopsys Verdi
MOUNTAIN VIEW, USA: Synopsys Inc. announced that SK Hynix Inc. has addressed their debug challenges by adopting the Synopsys VC Apps open application programming interfaces (APIs) to directly link their internally developed test generation technology to the industry-leading Synopsys Verdi debug solution and allow their design and verification teams to customize their debug experience and boost debug productivity.
Synopsys' VC Apps open APIs provide direct access to design environment and verification information stored in Verdi's open databases, which are in turn used by all leading simulation, emulation and formal verification solutions. With this native integration, SK Hynix engineers can save hours on each run and debug cycle.
"At SK Hynix, we had to find just the right balance of innovations from our technology partners with our own innovative processes in order to become the memory leader we are today," said Edward Kim, director of memory CAE at SK Hynix. "The productivity our engineers gain from deployment of VC Apps and standardized use of Verdi helps us to not only maintain that balance, but also reduce our costs and get working products to our customers faster."
Traditional methods for debugging data and results from internal or third-party tools involve either ad hoc manual steps and/or translation scripts that are both time-consuming and error-prone. VC Apps provides debug integration capabilities for CAD teams and tool developers, making it easy for individual users to further customize their debug flows and experience within Verdi.
With design and verification teams spending, on average, half of their time on debug, the time spent searching for commands and options or repeating common sequences of clicks and actions accumulates into substantial time and cost. The same APIs for Verdi databases and GUIs are accessible to all users, with clear open source examples and tutorials available on the VC Apps Exchange website and through the VC Apps Toolbox in Verdi.
"We collaborate closely with our semiconductor industry partners to ensure that debug remains as simple as possible despite the complexity of their chips and increased verification challenges," said Yu-Chin Hsu, VP of R&D, Synopsys Verification Group.
"We continue our significant investment in the open Verdi architecture, as well as in specialized technologies and methodologies for optimizing our customers' and partners' unique debug flows. VC Apps is one of the keys to unlocking the full power and flexibility that we have architected into both Verdi and now Verification Compiler product."
Synopsys' VC Apps open APIs provide direct access to design environment and verification information stored in Verdi's open databases, which are in turn used by all leading simulation, emulation and formal verification solutions. With this native integration, SK Hynix engineers can save hours on each run and debug cycle.
"At SK Hynix, we had to find just the right balance of innovations from our technology partners with our own innovative processes in order to become the memory leader we are today," said Edward Kim, director of memory CAE at SK Hynix. "The productivity our engineers gain from deployment of VC Apps and standardized use of Verdi helps us to not only maintain that balance, but also reduce our costs and get working products to our customers faster."
Traditional methods for debugging data and results from internal or third-party tools involve either ad hoc manual steps and/or translation scripts that are both time-consuming and error-prone. VC Apps provides debug integration capabilities for CAD teams and tool developers, making it easy for individual users to further customize their debug flows and experience within Verdi.
With design and verification teams spending, on average, half of their time on debug, the time spent searching for commands and options or repeating common sequences of clicks and actions accumulates into substantial time and cost. The same APIs for Verdi databases and GUIs are accessible to all users, with clear open source examples and tutorials available on the VC Apps Exchange website and through the VC Apps Toolbox in Verdi.
"We collaborate closely with our semiconductor industry partners to ensure that debug remains as simple as possible despite the complexity of their chips and increased verification challenges," said Yu-Chin Hsu, VP of R&D, Synopsys Verification Group.
"We continue our significant investment in the open Verdi architecture, as well as in specialized technologies and methodologies for optimizing our customers' and partners' unique debug flows. VC Apps is one of the keys to unlocking the full power and flexibility that we have architected into both Verdi and now Verification Compiler product."
Synopsys and Gowin Semiconductor ink multi-year OEM agreement for FPGA design software
MOUNTAIN VIEW, USA: Synopsys Inc. has announced a multi-year OEM agreement with Gowin Semiconductor for Synopsys Synplify Pro FPGA synthesis tools.
The agreement will enable Gowin customers to significantly improve synthesis runtimes and achieve higher quality of results for timing, area and power for Gowin GW2A/3S FPGAs. Gowin Semiconductor has partnered with Synopsys to integrate Synplify Pro into its GOWIN design suite for their GW2A/3S FPGAs.
"Our customers require a high performance, high-quality FPGA synthesis flow to help them implement their FPGA designs in hardware, while meeting tight project timelines," said Ning Song, chief technical officer and VP of FPGA software at Gowin Semiconductor.
"The integration of our FPGA software flow with Synplify Pro enables FPGA designers using our GW2A FPGA architecture to achieve the highest quality of results for timing, area and runtime."
Gowin's GW2A/3S FPGAs incorporate highly programmable logic, block SRAM and DSP blocks optimized for performance and power. The GW2A architecture is optimized with Synplify Pro synthesis software, providing designers with the highest performance results with fewer iterations.
Designers can take advantage of the wide range of device sizes and I/O capabilities to deliver products for consumer, industrial, communication and computing markets.
"Today's FPGA designs require advanced synthesis tools that deliver automation, faster turnaround times and more predictable timing closure," said John Koeter, VP of marketing for IP and prototyping at Synopsys.
"Synopsys Synplify FPGA synthesis software is the industry standard for producing high-performance, cost-effective FPGA designs. Integration of Synplify Pro with the GOWIN design suite will help Gowin customers quickly create optimized FPGA implementations that meet precise timing and quality requirements."
The agreement will enable Gowin customers to significantly improve synthesis runtimes and achieve higher quality of results for timing, area and power for Gowin GW2A/3S FPGAs. Gowin Semiconductor has partnered with Synopsys to integrate Synplify Pro into its GOWIN design suite for their GW2A/3S FPGAs.
"Our customers require a high performance, high-quality FPGA synthesis flow to help them implement their FPGA designs in hardware, while meeting tight project timelines," said Ning Song, chief technical officer and VP of FPGA software at Gowin Semiconductor.
"The integration of our FPGA software flow with Synplify Pro enables FPGA designers using our GW2A FPGA architecture to achieve the highest quality of results for timing, area and runtime."
Gowin's GW2A/3S FPGAs incorporate highly programmable logic, block SRAM and DSP blocks optimized for performance and power. The GW2A architecture is optimized with Synplify Pro synthesis software, providing designers with the highest performance results with fewer iterations.
Designers can take advantage of the wide range of device sizes and I/O capabilities to deliver products for consumer, industrial, communication and computing markets.
"Today's FPGA designs require advanced synthesis tools that deliver automation, faster turnaround times and more predictable timing closure," said John Koeter, VP of marketing for IP and prototyping at Synopsys.
"Synopsys Synplify FPGA synthesis software is the industry standard for producing high-performance, cost-effective FPGA designs. Integration of Synplify Pro with the GOWIN design suite will help Gowin customers quickly create optimized FPGA implementations that meet precise timing and quality requirements."
AMD Radeon supercharges Sid Meier’s Civilization: Beyond Earth with Mantle Graphics API
USA: AMD joins Firaxis Games in celebrating the release of Sid Meier’s Civilization: Beyond Earth, which features day-one support for AMD’s Mantle graphics API to enable top gaming performance for AMD Radeon graphics customers.
“AMD Radeon GPUs with Mantle are over a year ahead of other graphics companies in delivering high-throughput, high-efficiency graphics to gamers and developers,” said Matt Skynner, corporate VP and GM, Product and Platform Solutions Business Unit, AMD.
“As gamers settle in for a marathon session of Sid Meier’s Civilization: Beyond Earth, we’re proud that the potent combination of Mantle and the award-winning Graphics Core Next architecture effortlessly enable the definitive experience.”
Mantle is a “low-overhead” graphics API that can help improve performance for gamers by making better use of multi-core CPUs, streamlining game code execution, virtually eliminating software bottlenecks and utilizing GPU resources with incredible efficiency.
In performance testing, the AMD Radeon R9 290X GPU with Mantle rendered Sid Meier’s Civilization: Beyond Earth at higher frame rates than any other single-GPU graphics card. Gamers looking to secure Mantle’s blistering performance for their own empires can do so today with the purchase of an AMD Radeon R9 or R7 Series GPU starting at just $99.
“AMD Radeon GPUs with Mantle are over a year ahead of other graphics companies in delivering high-throughput, high-efficiency graphics to gamers and developers,” said Matt Skynner, corporate VP and GM, Product and Platform Solutions Business Unit, AMD.
“As gamers settle in for a marathon session of Sid Meier’s Civilization: Beyond Earth, we’re proud that the potent combination of Mantle and the award-winning Graphics Core Next architecture effortlessly enable the definitive experience.”
Mantle is a “low-overhead” graphics API that can help improve performance for gamers by making better use of multi-core CPUs, streamlining game code execution, virtually eliminating software bottlenecks and utilizing GPU resources with incredible efficiency.
In performance testing, the AMD Radeon R9 290X GPU with Mantle rendered Sid Meier’s Civilization: Beyond Earth at higher frame rates than any other single-GPU graphics card. Gamers looking to secure Mantle’s blistering performance for their own empires can do so today with the purchase of an AMD Radeon R9 or R7 Series GPU starting at just $99.
Mentor Graphics to host User2User 2014 India conference in Bangalore
BANGALORE, INDIA: Mentor Graphics Corp. announced that it will host its 10th annual User2User India conference on October 31, 2014 at Vivanta by Taj (the former Taj Residency), M.G.Road, Trinity Circle, Bangalore.
This year’s conference will feature keynote presentations from Walden C. Rhines, CEO and chairman, Mentor Graphics and Pradeep Vajram, president and CEO, Smartplay.
The conference includes an industry discussion on “Bringing together Indian and Multi-National Company Work - Cultures to Create the Next-Generation Organization” with panelists Pillalamarri Sridhar, MD, Maxlinear; Anuradha Srinivasan, research director, Intel Technologies India Pvt Ltd, Pradip A. Thaker, GM, India Operations and senior director (VLSI and H/W Engineering) for Geo Semiconductors; Himamshu Khasnis, CEO, Signalchip; and Walden C. Rhines, Mentor Graphics.
The Mentor Graphics User2User 2014 India conference is part of the annual Mentor Graphics international user conference series. This highly interactive, in-depth technical conference focuses on real world experiences using Mentor tools to design leading-edge products.
Attendees share with their colleagues their best practices, experiences, challenges, tips and tricks that they have learned using Mentor tools most effectively to design, develop and deploy high-quality products.
“Mentor’s User2User conference enables customers to network with one another, learn useful tips from company engineers and fellow users, and share best-practice methodologies,” said Hanns Windele, Mentor Graphics VP, Europe and India.
“Our goal is to provide users with everything they need to be productive with Mentor Graphics tools, and attendees report that they find their time at the event well spent.”
This year’s conference will feature keynote presentations from Walden C. Rhines, CEO and chairman, Mentor Graphics and Pradeep Vajram, president and CEO, Smartplay.
The conference includes an industry discussion on “Bringing together Indian and Multi-National Company Work - Cultures to Create the Next-Generation Organization” with panelists Pillalamarri Sridhar, MD, Maxlinear; Anuradha Srinivasan, research director, Intel Technologies India Pvt Ltd, Pradip A. Thaker, GM, India Operations and senior director (VLSI and H/W Engineering) for Geo Semiconductors; Himamshu Khasnis, CEO, Signalchip; and Walden C. Rhines, Mentor Graphics.
The Mentor Graphics User2User 2014 India conference is part of the annual Mentor Graphics international user conference series. This highly interactive, in-depth technical conference focuses on real world experiences using Mentor tools to design leading-edge products.
Attendees share with their colleagues their best practices, experiences, challenges, tips and tricks that they have learned using Mentor tools most effectively to design, develop and deploy high-quality products.
“Mentor’s User2User conference enables customers to network with one another, learn useful tips from company engineers and fellow users, and share best-practice methodologies,” said Hanns Windele, Mentor Graphics VP, Europe and India.
“Our goal is to provide users with everything they need to be productive with Mentor Graphics tools, and attendees report that they find their time at the event well spent.”
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