Synopsys' DesignWare universal DDR memory controller delivers up to 30 percent lower latency and increases system performance

MOUNTAIN VIEW, USA: Synopsys Inc. announced the release of its enhanced DesignWare® Universal DDR Memory Controller, which delivers up to 30 percent lower latency and offers up to 15 percent higher throughput than the previous generation controller. The DDR Memory Controller offers new features such as high-priority bypass and configurable 'look-ahead.'

The high-priority bypass option allows designers to improve latency by bypassing the scheduling algorithm, allowing immediate access to the DRAM. The configurable 'look-ahead' feature provides intelligent scheduling to maximize throughput by prioritizing out-of-order transactions to the DRAM, allowing designers to make trade-offs between area and performance. The Memory Controller also offers a DFI 2.1-compliant interface to the DDR PHY, delivers memory system performance of up to 2133 Mbps and supports the DDR3, DDR2, LPDDR and LPDDR2 SDRAM standards.

"As the leading supplier of SoCs for femtocells and small-cell base stations, we rely on Synopsys, a trusted IP vendor, to provide us with a high-quality DDR IP solution that further helps us differentiate our products in the market," said Will Robbins, vice-president of Silicon, Tools and Platforms at Picochip. "Synopsys' continued advancements in DDR IP allow us to reliably develop high-performance memory systems that are optimized for both throughput and latency."

"Synopsys is continually improving the performance and features of our DDR memory controller solutions," said John Koeter, vice president of marketing for IP and Systems at Synopsys. "By combining the best features of the previous-generation DesignWare Universal DDR memory controller with the best features of the Intelli™ architecture acquired from Virage Logic, we are able to significantly decrease the latency and improve throughput in this generation. With a proven track record of more than 250 DDR IP design wins amongst more than 200 customers, Synopsys offers designers a low-risk path to silicon success."

The DesignWare Universal DDR Memory Controller is part of Synopsys' comprehensive DesignWare DDR IP offering that consists of digital controllers and PHY IP supporting DDR, DDR2, DDR3, LPDDR and LPDDR2. The DesignWare DDR IP supports leading 130-nm, 90-nm, 65-nm, 55-nm, 45/40-nm and 32/28-nm technologies.

The enhanced version of the DesignWare Universal DDR Memory Controller single-port configuration is scheduled for availability in March 2011.